|
|
PDF CY62148G Data sheet ( Hoja de datos )
| Número de pieza | CY62148G | |
| Descripción | 4-Mbit (512K words x 8 bit) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY62148G (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
|
No Preview Available !
CY62148G MoBL®
4-Mbit (512K words × 8 bit) Static RAM
with Error-Correcting Code (ECC)
4-Mbit (512K words × 8 bit) Static RAM with Error-Correcting Code (ECC)
Features
■ High speed: 45 ns/55 ns
■ Ultra-low standby power
❐ Typical standby current: 3.5 μA
❐ Maximum standby current: 8.7 μA
■ Embedded ECC for single-bit error correction[1]
■ Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V
■ 1.0-V data retention
■ TTL-compatible inputs and outputs
■ Pb-free 32-pin SOIC and 32-pin TSOP II packages
Functional Description
CY62148G is a high-performance CMOS low-power (MoBL)
SRAM device with embedded ECC[1]. This device is offered
multiple pin configurations.
Device is accessed by asserting the chip enable (CE) input LOW.
Data writes are performed by asserting the Write Enable (WE)
input LOW, while providing the data on I/O0 through I/O7 and
address on A0 through A18 pins.
Data reads are performed by asserting the Output Enable (OE)
input and providing the required address on the address lines.
Read data is accessible on the I/O lines (I/O0 through I/O7).
All I/Os (I/O0 through I/O7) are placed in a HI-Z state when the
device is deselected (CE HIGH or control signal OE is
de-asserted).
See the Truth Table – CY62148G on page 12 for a complete
description of read and write modes.
The logic block diagrams are on page 2.
Logic Block Diagram – CY62148G
ECC ENCODER
DATAIN
DRIVERS
A0
A1
A2
A3
A4
A5
512K x 8
RAM ARRAY
A6
A7
A8
A9
COLUMN
DECODER
I/O0-I/O7
WE
OE
CE
Note
1. This device does not support automatic write-back on error detection.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-95415 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 10, 2016
1 page  
DC Electrical Characteristics (continued)
Over the operating range of –40 °C to 85 °C
Parameter
Description
ISB1[6]
ISB2[6]
Automatic power down
current – CMOS inputs;
VCC = 2.2 V to 3.6 V and
4.5 V to 5.5 V
Automatic power down
current – CMOS inputs
VCC = 1.65 V to 2.2 V
Automatic power down
current – CMOS inputs
VCC = 2.2 V to 3.6 V and
4.5 V to 5.5 V
Automatic power down
current – CMOS inputs
VCC = 1.65 V to 2.2 V
Test Conditions
CE1 > VCC – 0.2 V or CE2 < 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = fmax (address and data only),
f = 0 (OE, and WE), Max VCC
25 °C [7]
CE1 > VCC – 0.2 V or
CE2 < 0.2 V,
40 °C [7]
70 °C [7]
VIN > VCC – 0.2 V or
VIN < 0.2 V,
85 °C
f = 0, Max VCC
CE1 > VCC – 0.2 V or
CE2 < 0.2 V,
VIN > VCC – 0.2 V or
VIN < 0.2 V,
25 °C [7]
40 °C [7]
70 °C [7]
85 °C
f = 0, Max VCC
CY62148G MoBL®
45 ns / 55 ns
Min Typ Max
– – 8.7
Unit
μA
– – 10
– 3.5 3.7 μA
– – 4.8
––7
– – 8.7
– 3.5 4.3
––5
– – 7.5
– – 10
Notes
6. Chip enables (CE must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
7. The ISB2 limits at 25 °C, 40 °C, 70 °C, and typical limit at 85 °C are guaranteed by design and not 100% tested.
Document Number: 001-95415 Rev. *D
Page 5 of 17
5 Page 
CY62148G MoBL®
Switching Waveforms (continued)
Figure 7. Write Cycle No. 2 (CE Controlled) [27, 28]
tW C
ADDRESS
CE
WE
tS A
tAW
tSCE
tPWE
tH A
BHE /
BLE
tBW
OE
DATA I/O
ADDRESS
t HZOE
tSD tH D
D A T A IN V A L ID
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [27, 28, 29]
tWC
tSCE
CE
BHE /
BLE
WE
DATA I/O
tSA
tBW
tAW
tPWE
tHA
t HZWE
t LZW E
tSD tHD
DATA IN VALID
Notes
27. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
28. Data I/O is in HI-Z state if CE = VIH, or OE = VIH
29. The minimum write pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be sum of tHZWE and tSD.
Document Number: 001-95415 Rev. *D
Page 11 of 17
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet CY62148G.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY62148 | 512K x 8 MoBL Static RAM | Cypress Semiconductor |
| CY62148DV30 | 4-Mbit (512 K x 8) MoBL Static RAM | Cypress Semiconductor |
| CY62148E | 4-Mbit (512 K x 8) Static RAM | Cypress Semiconductor |
| CY62148ESL | 4-Mbit (512 K x 8) Static RAM | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |