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PDF AT84AS001 Data sheet ( Hoja de datos )
| Número de pieza | AT84AS001 | |
| Descripción | 12-bit 500 Msps ADC | |
| Fabricantes | e2v | |
| Logotipo |  |
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AT84AS001
12-bit 500 Msps ADC
Datasheet
1. Main Features
• 12-bit Resolution
• 500 Msps Sampling Rate
• Low Clock Latency (Two Clock Cycles)
• 1.1 Vpp Full Scale Analog input Range (Aids in Amplifier Interface)
• AC or DC Coupled Analog Input with External Control
• Constant Input Impedance
• Differential 100 PECL/LVDS Compatible Clock Inputs
• LVDS Output Compatibility (100)
• 3-wire Serial Bus Programming Interface
– 16-bit Data, 3-bit Address
– Gain (–1.5 dB/+1.2 dB Full-scale) Digital Control
– Offset Digital Control (±45 LSB)
– Standby Mode
– Internal Static Built-In Test (BIT)
• Synchronous Reset Input
• Low Power Consumption: 2.4W
• Power Supply: 5V (Analog), 3.3V (Digital, Output)
• EBGA 192 Package
• Evaluation Board AT84AS001TP-EB
2. Performances
• 1 GHz Full Power Input Bandwidth (–3 dB)
• Band Flatness 0.5 dB (from DC Up to 200 MHz)
• 9.8-bit ENOB (at FIN = 250 MHz)
• Single Tone Performances (–1 dBFS)
– SFDR = 75 dBc at Fs = 500 Msps, Fin = 250 MHz, –1 dB input level
– SFDR = 73 dBc at Fs = 500 Msps, Fin = 394 MHz, –1 dB input level
– SNR = 61 dBc at Fs = 500 Msps, Fin = 250 MHz, –1 dB input level
• Dual Tone Performances (–7 dBFS)
– IMD3 = –78 dBFS at Fs = 500 Msps, Fin1 = 240 MHz, Fin2 = 250 MHz
• DNL = ±0.8 LSB; INL = ±2 LSB (Typical)
• Low Bit Error Rate (10 -14) at Fs = 500 Msps
3. Screening
• Temperature Range:
– Commercial C Grade 0C < Tamb < 70C
– Industrial V Grade –40C < Tamb < 85C
e2v semiconductors SAS 2014
Visit our website: www.e2v.com
for the latest version of the datasheet
0858D–BDC–06/14
1 page  
AT84AS001
Table 6-3. Electrical Characteristics (Continued)
Parameter
Test Level
Reset Input
Logic compatibility for RESET input
2.5V PECL differential logical level
Logic 0 voltage
Logic 1 voltage
Swing (peak-to-peak)
4
3.3V PECL differential logical level
Logic 0 voltage
Logic 1 voltage
Swing (peak-to-peak)
4
LVDS differential logical level
Logic 0 voltage
Logic 1 voltage
Swing (peak-to-peak)
1
Differential logical levels compatibility
Logic 0 voltage
Logic 1 voltage
Swing (peak-to-peak)
4
Symbol
VIL
VIH
|VIL – VIHI
VIL
VIH
|VIL – VIH|
VIL
VIH
|VIL – VIH|
VIL
VIH
|VIL –VIH|
Min Typ Max
PECL/LVDS
0.5 0.68
1
1.3 1.48 1.9
0.8
1.3 1.48 1.9
2 2.28 2.6
0.8
0.925
1.1
1.2
1.3 1.4 1.475
0.3
0 VCCD –0.1
1.3 VCCD +0.1
0.2 VCCD +0.1
Unit
V
V
V
V
V
V
V
V
V
V
V
V
Table 6-4. DC Accuracy
Parameter
DC Accuracy
No missing code
Differential non-linearity (no missing code
guaranteed)
Integral non-linearity
Amplitude error (part-to-part) for output
code = 4096 (FS = input full-scale)
Gain error drift vs.VCCA
Gain error drift vs.temperature
Input offset code
Input offset code drift over temperature
range
Test Level
1
1
1
1
1
4
1
4
Symbol
DNL
INL
Min Typ Max
Guaranteed over specified
temperature range
0.8
±2
±5
10
20
2048
±4
Unit
LSB
LSB
%FS
LSB/V
mLSB/C
LSB
LSB
e2v semiconductors SAS 2014
0858D–BDC–06/14
5
5 Page 
AT84AS001
8. Typical Characteristics
Figure 8-1. SFDR Performance versus Fin at Fs = 500 Msps (–1 dBFS Input Signal)
-50.00
-55.00
-60.00
-65.00
-70.00
-75.00
-80.00
0
100 200 300 400 500 600
Fin (MHz)
Figure 8-2. Single-tone Spectrum in First Nyqusit, Fs = 500 Msps, Fin = 248 MHz , –1 dBFS Input
Signal
0
H1 = 248 MHz
-20
SFDR = -75 dBc
-40
dBm -60
-80
H2 = Fs - 2Fin = 4 MHz
-100
-120
0
50 100 150 200 250
Fin (MHz)
e2v semiconductors SAS 2014
0858D–BDC–06/14
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT84AS001.PDF ] | |
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