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PDF AK4641 Data sheet ( Hoja de datos )
| Número de pieza | AK4641 | |
| Descripción | 16-BIT CODEC | |
| Fabricantes | Asahi Kasei Microsystems | |
| Logotipo |  |
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ASAHI KASEI
[AK4641]
AK4641
16-Bit ∆Σ CODEC with Bluetooth Interface
GENERAL DESCRIPTION
The AK4641 is targeted at PDA and other low-power, small size applications. It features a 16bit Stereo
CODEC with a built-in Microphone-Amplifier and 16bit Mono CODEC for Bluetooth Interface. Input
circuits include Microphone-Amplifier and ALC (Auto Level Control) circuit. The AK4641 is available in a
36pin QFN, utilizing less board space than competitive offerings.
FEATURES
1. Recording Function of 16bit Stereo CODEC
• Mono Input
• 2 to 1 Selector (Internal and External MIC)
• 1st MIC Amplifier: +20dB or 0dB
• 2nd Amplifier with ALC: +27.5dB ∼ −8dB, 0.5dB Step
• ADC Performance: S/(N+D): 81dB, S/N: 86dB
• Sampling Rate: 7kHz ∼ 48kHz
• Audio Interface Format: I2S, 16bit MSB justified
2. Playback Function of 16bit Stereo CODEC
• Digital De-emphasis Filter (tc=50/15µs, fs=32kHz, 44.1kHz, 48kHz)
• Digital Volume (0dB ∼ −127dB, 0.5dB Step, Mute)
• 5 Band Equalizer
• Stereo Line Output
- Performance: S/(N+D): 86dB, S/N: 90dB
• Mono Line Output
- Differential Output
- Performance: S/(N+D): 86dB, S/N: 93dB
• AUX Input
- Differential Input
- +24dB ∼ −21dB, 3dB step
• Sampling Rate: 7kHz ∼ 48kHz
• Audio Interface Format: I2S, 16bit MSB justified, 16bit LSB justified
3. 16bit Mono CODEC
• Analog Mix Path for Bluetooth Interface
• Sample Rate: 8kHz ∼ 16kHz
• Audio Interface Format: Short/Long Frame, I2S, 16bit MSB justified
4. Power Management
5. Master Clock: 1.792MHz ∼ 12.288MHz
6. Control mode: I2C Bus
7. Ta = −20 ∼ 85°C
8. Power Supply: 2.6V∼ 3.6V (typ. 3.3V)
9. Power Supply Current: 17mA
10. Package: 36pin QFN (0.5mm pitch)
MS0301-E-02
-1-
2005/05
1 page  
ASAHI KASEI
[AK4641]
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS, BVSS =0V; Note 1)
Parameter
Symbol
min
Power Supplies: Analog
AVDD
−0.3
Digital
DVDD
−0.3
16bit Mono CODEC
BVDD
−0.3
|AVSS – DVSS| (Note 2)
∆GND1
-
|AVSS – BVSS| (Note 2)
∆GND2
-
Input Current, Any Pin Except Supplies
IIN -
Analog Input Voltage
VINA
−0.3
Digital Input Voltage
VIND
−0.3
Ambient Temperature (powered applied)
Ta −20
Storage Temperature
Tstg −65
Note 1. All voltages with respect to ground.
Note 2. AVSS, DVSS and BVSS must be connected to the same analog ground plane.
max
4.6
4.6
4.6
0.3
0.3
±10
AVDD+0.3
DVDD+0.3
85
150
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Units
V
V
V
V
V
mA
V
V
°C
°C
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS, BVSS=0V; Note 1)
Parameter
Symbol
min typ
Power Supplies Analog
AVDD
2.6 3.3
(Note 3) Digital
DVDD
2.6 3.3
16bit Mono CODEC
BVDD
2.6 3.3
Differences
AVDD−BVDD
−0.1
0
AVDD−DVDD
−0.3
0
BVDD−DVDD
−0.3
0
Note 1. All voltages with respect to ground.
Note 3. The power up sequence between AVDD, DVDD and BVDD is not critical.
* AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
max Units
3.6 V
3.6 V
3.6 V
+0.1 V
+0.3 V
+0.3 V
MS0301-E-02
-5-
2005/05
5 Page 
ASAHI KASEI
[AK4641]
Parameter
16bit Mono CODEC Interface Timing:
SYNC Timing
Frequency (PLL Lock Range)
Serial Interface Timing at Short/long Frame Sync
BBICK Frequency
BBICK Period
BBICK duty cycle
BBICK Pulse Width Low
Pulse Width High
BSYNC Edge to BBICK “↓ ”
BBICK “↓ ” to BSYNC Edge
BSYNC to BSDTO (MSB) (Except Short Frame)
BBICK “↑ ” to BSDTO
BSDTI Hold Time
BSDTI Setup Time
BSYNC Pulse Width Low
Pulse Width High
Serial Interface Timing at MSB justified and I2S
BBICK Frequency
BBICK Period
BBICK duty cycle
BBICK Pulse Width Low
Pulse Width High
BSYNC Edge to BBICK “↑ ”
BBICK “↑ ” to BSYNC Edge
BSYNC to BSDTO (MSB) (Except I2S mode)
BBICK “↓ ” to BSDTO
BSDTI Hold Time
BSDTI Setup Time
BSYNC Duty Cycle
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 21)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Reset Timing
PDN Pulse Width
(Note 22)
PMADC “↑” to SDTO valid (Note 23)
PMAD2 “↑” to BSDTO valid (Note 24)
Symbol
Bfs
fBBCK
tBBCK
tBDUT
tBBCKL
tBBCKH
tBSYB
tBBSY
tBSYD
tBBSD
tBSDH
tBSDS
tBBSL
tBBSH
fBBCK
tBBCK
tBDUT
tBBCKL
tBBCKH
tBSYB2
tBBSY2
tBSYD2
tBBSD2
tBSDH2
tBSDH2
BDuty2
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
TSU:STO
tSP
tPD
tPDV
tBPDV
min
8
128
488
200
200
50
50
50
50
3300
440
256
488
200
200
50
50
50
50
45
-
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
0.6
0
150
typ
-
50
50
50
2081
1057
Note 21. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 22. The AK4641 can be reset by the PDN pin = “L”.
Note 23. This is the count of LRCK “↑” from the PMADC bit = “1”.
Note 24. This is the count of BSYNC “↑” from the PMAD2 bit = “1”.
max Units
16
2048
80
80
2048
80
80
55
400
-
-
-
-
-
-
-
0.3
0.3
-
50
kHz
kHz
ns
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
kHz
ns
%
ns
ns
ns
ns
ns
ns
ns
ns
%
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
1/fs
1/Bfs
Purchase of Asahi Kasei Microsystems Co., Ltd I2C components conveys a license under the Philips
I2C patent to use the components in the I2C system, provided the system conform to the I2C
specifications defined by Philips.
MS0301-E-02
- 11 -
2005/05
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AK4641.PDF ] | |
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