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PDF DS90CP22 Data sheet ( Hoja de datos )
| Número de pieza | DS90CP22 | |
| Descripción | 2X2 800 Mbps LVDS Crosspoint Switch | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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March 2000
DS90CP22
2X2 800 Mbps LVDS Crosspoint Switch
General Description
DS90CP22 is a 2x2 crosspoint switch utilizing LVDS (Low
Voltage Differential Signaling) technology for low power, high
speed operation. Data paths are fully differential from input
to output for low noise generation and low pulse width distor-
tion. The non-blocking design allows connection of any input
to any output or outputs. LVDS I/O enable high speed data
transmission for point-to-point interconnects. This device
can be used as a high speed differential crosspoint, 2:1 mux,
1:2 demux, repeater or 1:2 signal splitter. The mux and de-
mux functions are useful for switching between primary and
backup circuits in fault tolerant systems. The 1:2 signal split-
ter and 2:1 mux functions are useful for distribution of serial
bus across several rack-mounted backplanes.
The DS90CP22 accepts LVDS signal levels, LVPECL levels
directly or PECL with attenuation networks.
The individual LVDS outputs can be put into TRI-STATE by
use of the enable pins.
For more details, please refer to the Application Information
section of this datasheet.
Features
n Low jitter 800 Mbps fully differential data path
n 75 ps (typ) of pk-pk jitter with PRBS = 223−1 data
pattern at 800 Mbps
n Single +3.3 V Supply
n Less than 330 mW (typ) total power dissipation
n Non-blocking ’’Switch Architecture’’
n Balanced output impedance
n Output channel-to-channel skew is 35 ps (typ)
n Configurable as 2:1 mux, 1:2 demux, repeater or 1:2
signal splitter
n LVDS receiver inputs accept LVPECL signals
n Fast switch time of 1.2ns (typ)
n Fast propagation delay of 1.3ns (typ)
n Receiver input threshold < ±100 mV
n 16 lead SOIC package
n Inter-operates with ANSI/TIA/EIA-644-1995 LVDS
standard
Connection Diagram
DS101053-5
Order Number DS90CP22M-8
See NS Package Number M16A
DS101053-10
Diff. Output Eye-Pattern in 1:2 split mode @ 800 Mbps
Conditions: 3.3 V, PRBS = 223−1 data pattern,
VID = 300mV, VCM = +1.2 V, 200 ps/div, 100 mV/div
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation DS101053
www.national.com
1 page  
AC Timing Diagrams (Continued)
FIGURE 4. LVDS Output Load
DS101053-6
FIGURE 5. LVDS Output Transition Time
DS101053-9
DS101053-7
FIGURE 6. Propagation Delay Low-to-High and High-to-Low
DS101053-8
FIGURE 7. Output Channel-to-Channel Skew in 1:2 splitter mode
5 www.national.com
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet DS90CP22.PDF ] | |
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