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PDF DS90CR211MTD Data sheet ( Hoja de datos )
| Número de pieza | DS90CR211MTD | |
| Descripción | 21-Bit Channel Link | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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July 1997
DS90CR211/DS90CR212
21-Bit Channel Link
General Description
The DS90CR211 transmitter converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fourth LVDS link. Every
cycle of the transmit clock 21 bits of input data are sampled
and transmitted. The DS90CR212 receiver converts the
LVDS data streams back into 21 bits of CMOS/TTL data. At
a transmit clock frequency of 40 MHz, 21 bits of TTL data are
transmitted at a rate of 280 Mbps per LVDS data channel.
Using a 40 MHz clock, the data throughput is 840
Mbit/s(105 Mbyte/s).
The multiplexing of the data lines provides a substantial
cable reduction. Long distance parallel single-ended buses
typically require a ground wire per active signal (and have
very limited noise rejection capability). Thus, for a 21-bit wide
data bus and one clock, up to 44 conductors are required.
With the Channel Link chipset as few as 9 conductors (3
data pairs, 1 clock pair and a minimum of one ground) are
needed. This provides a 80% reduction in required cable
width, providing a system cost savings, reduces connector
physical size, and reduces shielding requirements due to the
cables smaller form factor.
The 21 CMOS/TTL inputs can support a variety of signal
combinations. For example, 5 4-bit nibbles plus 1 control, or
2 9-bit (byte + parity) and 3 control.
Features
n Narrow bus reduces cable size and cost
n ±1V Common mode range (ground shifting)
n 290 mV swing LVDS data transmission
n 840 Mbit/s data throughput
n Low swing differential current mode drivers reduce EMI
n Rising edge data strobe
n Power down mode
n Offered in low profile 48-lead TSSOP package
Block Diagrams
DS90CR211
DS90CR212
Order Number DS90CR211MTD
See NS Package Number MTD48
DS012637-27
Order Number DS90CR212MTD
See NS Package Number MTD48
DS012637-1
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS012637
www.national.com
1 page  
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
CLHT
CHLT
RCOP
RSKM
RCOH
RCOL
RSRC
RHRC
RCCD
RPLLS
RPDD
Parameter
CMOS/TTL Low-to-High Transition Time (Figure 3)
CMOS/TTL High-to-Low Transition Time (Figure 3)
RxCLK OUT Period (Figure 7)
Receiver Skew Margin (Note 6)
f = 20 MHz
VCC = 5V, TA = 25˚C (Figure 17)
RxCLK OUT High Time (Figure 7)
f = 40 MHz
f = 20 MHz
f = 40 MHz
RxCLK OUT Low Time (Figure 7)
f = 20 MHz
f = 40 MHz
RxCLK Setup to RxCLK OUT (Figure 7)
f = 20 MHz
f = 40 MHz
RxCLK Hold to RxCLK OUT (Figure 7)
f = 20 MHz
f = 40 MHz
RxCLK IN to RxCLK OUT Delay @ 25˚C, VCC = 5.0V (Figure 9)
Receiver Phase Lock Loop Set (Figure 11)
Receiver Powerdown Delay (Figure 15)
Min Typ Max Units
3.5 6.5
ns
2.7 6.5
ns
25 T 50
ns
1.1 ns
700 ps
19 ns
6 ns
21.5
ns
10.5
ns
14 ns
4.5 ns
16 ns
6.5 ns
7.6
11.9
ns
10 ms
1 µs
Note 6: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account for transmitter output skew(TCCS)
and the setup and hold time (internal data sampling window), allowing LVDS cable skew dependent on type/length and source clock(TxCLK IN) jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle).
AC Timing Diagrams
FIGURE 1. “WORST CASE” Test Pattern
DS012637-4
DS012637-5
FIGURE 2. DS90CR211 (Transmitter) LVDS Output Load and Transition Timing
DS012637-6
DS012637-7
FIGURE 3. DS90CR212 (Receiver) CMOS/TTL Output Load and Transition Timing
5
DS012637-8
www.national.com
5 Page 
Applications Information (Continued)
to the layout of differential lines. Lines of a differential pair
should always be adjacent to eliminate noise interference
from other signals and take full advantage of the noise can-
celing of the differential signals. The board designer should
also try to maintain equal length on signal traces for a given
differential pair. As with any high speed design, the imped-
ance discontinuities should be limited (reduce the numbers
of vias and no 90 degree angles on traces). Any discontinui-
ties which do occur on one signal line should be mirrored in
the other line of the differential pair. Care should be taken to
ensure that the differential trace impedance match the differ-
ential impedance of the selected physical media (this imped-
ance should also match the value of the termination resistor
that is connected across the differential pair at the receiver’s
input). Finally, the location of the CHANNEL LINK TxOUT/
RxIN pins should be as close as possible to the board edge
so as to eliminate excessive pcb runs. All of these consider-
ations will limit reflections and crosstalk which adversely ef-
fect high frequency performance and EMI.
FIGURE 18. LVDS Serialized Link Termination
DS012637-20
UNUSED INPUTS: All unused inputs at the TxW inputs of
the transmitter must be tied to ground. All unused outputs at
the RxOUT outputs of the receiver must then be left floating.
TERMINATION: Use of current mode drivers requires a ter-
minating resistor across the receiver inputs. The CHANNEL
LINK chipset will normally require a single 100Ω resistor be-
tween the true and complement lines on each differential
pair of the receiver input. The actual value of the termination
resistor should be selected to match the differential mode
characteristic impedance (90Ω to 120Ω typical) of the cable.
Figure 18 shows an example. No additional pull-up or
pull-down resistors are necessary as with some other differ-
ential technologies such as PECL. Surface mount resistors
are recommended to avoid the additional inductance that ac-
companies leaded resistors. These resistors should be
placed as close as possible to the receiver input pins to re-
duce stubs and effectively terminate the differential lines.
DECOUPLING CAPACITORS: Bypassing capacitors are
needed to reduce the impact of switching noise which could
limit performance. For a conservative approach three
parallel-connected decoupling capacitors (Multi-Layered Ce-
ramic type in surface mount form factor) between each VCC
and the ground plane(s) are recommended. The three ca-
pacitor values are 0.1 µF, 0.01µF and 0.001 µF. An example
is shown in Figure 19. The designer should employ wide
traces for power and ground and ensure each capacitor has
its own via to the ground plane. If board space is limiting the
number of bypass capacitors, the PLL VCC should receive
the most filtering/bypassing. Next would be the LVDS VCC
pins and finally the logic VCC pins.
DS012637-21
FIGURE 19. CHANNEL LINK
Decoupling Configuration
CLOCK JITTER: The CHANNEL LINK devices employ a
PLL to generate and recover the clock transmitted across the
LVDS interface. The width of each bit in the serialized LVDS
data stream is one-seventh the clock period. For example, a
40 MHz clock has a period of 25 ns which results in a data bit
width of 3.57 ns. Differential skew (∆t within one differential
pair), interconnect skew (∆t of one differential pair to an-
other) and clock jitter will all reduce the available window for
sampling the LVDS serial data streams. Care must be taken
to ensure that the clock input to the transmitter be a clean
low noise signal. Individual bypassing of each VCC to ground
will minimize the noise passed on to the PLL, thus creating a
low jitter LVDS clock. These measures provide more margin
for channel-to-channel skew and interconnect skew as a part
of the overall jitter/skew budget.
11 www.national.com
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| PDF Descargar | [ Datasheet DS90CR211MTD.PDF ] | |
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