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PDF DS90CR561 Data sheet ( Hoja de datos )
| Número de pieza | DS90CR561 | |
| Descripción | LVDS 18-Bit Color Flat Panel Display (FPD) Link | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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July 1997
DS90CR561/DS90CR562
LVDS 18-Bit Color Flat Panel Display (FPD) Link
General Description
The DS90CR561 transmitter converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fourth LVDS link. Every
cycle of the transmit clock 21 bits of input data are sampled
and transmitted. The DS90CR562 receiver converts the
LVDS data streams back into 21 bits of CMOS/TTL data. At
a transmit clock frequency of 40 MHz, 18 bits of RGB data
and 3 bits of LCD timing and control data (FPLINE, FP-
FRAME, DRDY) are transmitted at a rate of 280 Mbps per
LVDS data channel. Using a 40 MHz clock, the data through-
put is 105 Megabytes per second. These devices are offered
with rising edge data strobes for convenient interface with a
variety of graphics and LCD panel controllers.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
n Up to 105 Megabyte/sec bandwidth
n Narrow bus reduces cable size and cost
n 290 mV swing LVDS devices for low EMI
n Low power CMOS design
n Power-down mode
n PLL requires no external components
n Low profile 48-lead TSSOP package
n Rising edge data strobe
n Compatible with TIA/EIA-644 LVDS standard
Block Diagrams
DS90CR561
DS90CR562
DS012470-27
Order Number DS90CR561MTD
See NS Package Number MTD48
Order Number DS90CR562MTD
See NS Package Number MTD48
DS012470-1
APPLICATION
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS012470
DS012470-2
www.national.com
1 page  
Transmitter Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
TPDD Transmitter Powerdown Delay (Figure 15)
Note 5: This limit based on bench characterization.
Min Typ Max Units
100 ns
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
CLHT
CHLT
RCOP
RSKM
RCOH
RCOL
RSRC
RHRC
RCCD
RPLLS
RPDD
Parameter
CMOS/TTL Low-to-High Transition Time (Figure 4)
CMOS/TTL High-to-Low Transition Time (Figure 4)
RxCLK OUT Period (Figure 8)
Receiver Skew Margin (Note 6)
f = 20 MHz
VCC = 5V, TA = 25˚C (Figure 18)
RxCLK OUT High Time (Figure 8)
f = 40 MHz
f = 20 MHz
f = 40 MHz
RxCLK OUT Low Time (Figure 8)
f = 20 MHz
f = 40 MHz
RxCLK Setup to RxCLK OUT (Figure 8)
f = 20 MHz
f = 40 MHz
RxCLK Hold to RxCLK OUT (Figure 8)
f = 20 MHz
f = 40 MHz
RxCLK IN to RxCLK OUT Delay @ 25˚C,
VCC = 5.0V (Figure 10)
Receiver Phase Lock Loop Set (Figure 12)
Receiver Powerdown Delay (Figure 16)
Min Typ Max Units
3.5 6.5
ns
2.7 6.5
ns
25 T 50
ns
1.1 ns
700 ps
19 ns
6 ns
21.5
ns
10.5
ns
14 ns
4.5 ns
16 ns
6 ns
7.6 11.9 ns
10 ms
1 µs
Note 6: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account for transmitter output skew (TCCS)
and the setup and hold time (internal data sampling window), allowing LVDS cable skew dependant on the type/length and source clock (TxCLK IN) jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle).
AC Timing Diagrams
FIGURE 1. “Worst Case” Test Pattern
DS012470-5
5 www.national.com
5 Page 
DS90CR561 Pin Description — FPD Link Transmitter (Continued)
Pin Name
VCC
GND
PLL VCC
PLL GND
LVDS VCC
LVDS GND
I/O No.
I4
I5
I1
I2
I1
I3
Power supply pins for TTL inputs
Ground pins for TTL inputs
Power supply pin for PLL
Ground pins for PLL
Power supply pin for LVDS outputs
Ground pins for LVDS outputs
Description
DS90CR562 Pin Description — FPD Link Receiver
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
FPSHIFT OUT
PWR DOWN
VCC
GND
PLL VCC
PLL GND
LVDS VCC
LVDS GND
I/O No.
I3
I3
O 21
I1
I1
O1
I1
I4
I5
I1
I2
I1
I3
Description
Positive LVDS differential data inputs
Negative LVDS differential data inputs
TTL level outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines (FPLINE,
FPFRAME, DRDY). (Also referred to as HSYNC, VSYNC and DATA ENABLE.)
Positive LVDS differential clock input
Negative LVDS differential clock input
TTL level clock output. The rising edge acts as data strobe.
TTL level input. Assertion (low input) maintains the receiver outputs in the previous state.
Power supply pins for TTL outputs
Ground pins for TTL outputs
Power supply for PLL
Ground pin for PLL
Power supply pin for LVDS inputs
Ground pins for LVDS inputs
11 www.national.com
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet DS90CR561.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DS90CR561 | LVDS 18-Bit Color Flat Panel Display (FPD) Link | National Semiconductor |
| DS90CR561 | DS90CR561/DS90CR562 LVDS 18-Bit Color Flat Panel Display (FPD) Link (Rev. B) |  Texas Instruments |
| DS90CR561MTD | LVDS 18-Bit Color Flat Panel Display (FPD) Link | National Semiconductor |
| DS90CR562 | DS90CR561/DS90CR562 LVDS 18-Bit Color Flat Panel Display (FPD) Link (Rev. B) | Texas Instruments |
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