|
|
PDF DS90CR581 Data sheet ( Hoja de datos )
| Número de pieza | DS90CR581 | |
| Descripción | LVDS Transmitter 24-Bit Color Flat Panel Display (FPD) Link | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de DS90CR581 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
|
No Preview Available !
May 1998
DS90CR581
LVDS Transmitter 24-Bit Color Flat Panel Display (FPD)
Link
General Description
The DS90CR581 transmitter converts 28 bits of CMOS/TTL
data into four LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in par-
allel with the data streams over a fifth LVDS link. Every cycle
of the transmit clock 28 bits of input data are sampled and
transmitted. At a transmit clock frequency of 40 MHz, 24 bits
of RGB data and 4 bits of LCD timing and control data
(FPLINE, FPFRAME, DRDY, CNTL) are transmitted at a rate
of 280 Mbps per LVDS data channel. Using a 40 MHz clock,
the data throughput is 140 Megabytes per second. This
transmitter is intended to interface to any of the FPD Link re-
ceivers.
The chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
n Up to 140 Megabyte/sec Bandwidth
n Narrow bus reduces cable size and cost
n 290 mV swing LVDS devices for low EMI
n Low power CMOS design
n Power down mode
n PLL requires no external components
n Low profile 56-lead TSSOP package
n Rising edge data strobe
n Compatible with TIA/EIA-644 LVDS standard
Block Diagrams
DS90CR581
Order Number DS90CR581MTD
See NS Package Number MTD56
DS012487-29
Application
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS012487
DS012487-2
www.national.com
1 page  
AC Timing Diagrams (Continued)
DS012487-16
Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 8: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 9: Figure 1 and Figure 2 show a rising edge data strobe (TxCLK IN/RxCLK OUT).
Note 10: Recommended pin to signal mapping. Customer may choose to define differently.
FIGURE 2. “16 Grayscale” Test Pattern (Notes 7, 8) (Note 9) (Note 10)
DS012487-8
DS012487-9
FIGURE 3. DS90CR581 (Transmitter) LVDS Output Load and Transition Timing
5 www.national.com
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet DS90CR581.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DS90CR581 | LVDS Transmitter 24-Bit Color Flat Panel Display (FPD) Link | National Semiconductor |
| DS90CR581 | DS90CR581 LVDS Transmitter 24-Bit Color Flat Panel Display (FPD) Link (Rev. B) |  Texas Instruments |
| DS90CR581MTD | LVDS Transmitter 24-Bit Color Flat Panel Display (FPD) Link | National Semiconductor |
| DS90CR583 | LVDS 24-Bit Color Flat Panel Display (FPD) Link65 MHz | National Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |