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PDF DS90CR583 Data sheet ( Hoja de datos )
| Número de pieza | DS90CR583 | |
| Descripción | LVDS 24-Bit Color Flat Panel Display (FPD) Link65 MHz | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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July 1997
DS90CR583/DS90CR584
LVDS 24-Bit Color Flat Panel Display (FPD) Link—
65 MHz
General Description
The DS90CR583 transmitter converts 28 bits of CMOS/TTL
data into four LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in par-
allel with the data streams over a fifth LVDS link. Every cycle
of the transmit clock 28 bits of input data are sampled and
transmitted. The DS90CR584 receiver converts the LVDS
data streams back into 28 bits of CMOS/TTL data. At a trans-
mit clock frequency of 65 MHz, 24 bits of RGB data and 4
bits of LCD timing and control data (FPLINE, FPFRAME,
DRDY, CONTROL) are transmitted at a rate of 455 Mbps per
LVDS data channel. Using a 65 MHz clock, the data through-
put is 227 Mbytes per second. These devices are offered
with rising edge data strobes for convenient interface with a
variety of graphics and LCD panel controllers.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
n 20 to 65 MHz shift clk support
n Up to 227 Mbytes/s bandwidth
n Cable size is reduced to save cost
n 290 mV swing LVDS devices for low EMI
n Low power CMOS design (< 550 mW typ)
n Power-down mode saves power (< 0.25 mW)
n PLL requires no external components
n Low profile 56-lead TSSOP package
n Rising edge data strobe
n Compatible with TIA/EIA-644 LVDS standard
n Single pixel per clock XGA (1024 x 768)
n Supports VGA, SVGA, XGA and higher
n 1.8 Gbps throughput
Block Diagrams
DS90CR583
DS90CR584
DS012618-2
Order Number DS90CR583MTD
See NS Package Number MTD56
DS012618-1
Order Number DS90CR584MTD
See NS Package Number MTD56
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS012618
www.national.com
1 page  
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
CLHT
CHLT
RCOP
RCOH
RCOL
RSRC
RHRC
RCCD
RPLLS
RSKM
RPDD
Parameter
CMOS/TTL Low-to-High Transition Time (Figure 4)
CMOS/TTL High-to-Low Transition Time (Figure 4)
RxCLK OUT Period
RxCLK OUT High Time
RxCLK OUT Low Time
RxOUT Setup to RxCLK OUT
RxOUT Hold to RxCLK OUT
RxCLK IN to RxCLK OUT Delay @ 25˚C, VCC = 5.0V
(Figure 10)
Receiver Phase Lock Loop Set (Figure 12)
RxIN Skew Margin (Note 6) (Figure 14)
Receiver Powerdown (Figure 17)
f = 65 MHz
f = 65 MHz
f = 65 MHz
f = 65 MHz
VCC = 5V, TA =25˚C
Min Typ Max Units
2.5 4.0
ns
2.0 3.5
ns
15 T 50 ns
3.8 5
ns
7.8 9
ns
2.5 4.2
ns
4.0 5.2
ns
6.4
10.7
ns
10 ms
600 ps
1 µs
Note 6: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output skew (TCCS)
and the setup and hold time (internal data sampling window), allowing for LVDS cable skew dependent on type/length and source clock (TxCLK IN) jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle)
AC Timing Diagrams
FIGURE 1. “Worst Case” Test Pattern
DS012618-4
5 www.national.com
5 Page 
DS90CR583 Pin Descriptions — FPD Link Transmitter (Continued)
Pin Name
GND
PLL VCC
PLL GND
LVDS VCC
LVDS GND
I/O No.
I5
I1
I2
I1
I3
Ground pins for TTL inputs
Power supply pin for PLL
Ground pins for PLL
Power supply pin for LVDS outputs
Ground pins for LVDS outputs
Description
DS90CR584 Pin Descriptions — FPD Link Receiver
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
FPSHIFT
OUT
PWR DOWN
VCC
GND
PLL VCC
PLL GND
LVDS VCC
LVDS GND
I/O No.
I4
I4
O 28
I1
I1
O1
I1
I4
I5
I1
I2
I1
I3
Description
Positive LVDS differential data inputs
Negative LVDS differential data inputs
TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE,
FPFRAME, DRDY and CNTL (also referred to as HSYNC, VSYNC, Data Enable, CNTL)
Positive LVDS differential clock input
Negative LVDS differential clock input
TTL level clock output. The falling edge acts as data strobe
TTL level input. Assertion (low input) maintains the receiver outputs in the previous state
Power supply pins for TTL outputs
Ground pins for TTL outputs
Power supply for PLL
Ground pin for PLL
Power supply pin for LVDS inputs
Ground pins for LVDS inputs
Connection Diagrams
DS012618-22
11
DS012618-23
www.national.com
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet DS90CR583.PDF ] | |
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