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PDF SM9103M Data sheet ( Hoja de datos )
| Número de pieza | SM9103M | |
| Descripción | DVDRAM Head Amplifier LSI | |
| Fabricantes | Nippon Precision Circuits Inc | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SM9103M (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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NIPPON PRECISION CIRCUITS INC.
SM9103M
DVDRAM Head Amplifier LSI
OVERVIEW
The SM9103M is a photodiode photoelectric cur-
rent-to-voltage conversion head amplifier LSI for
optical disk pickups in DVDRAM/DVDROM equip-
ment. It sums the photodiode current data signals and
then converts the signals to a differential signal for
output. The output tracking servo and focusing servo
signals are derived from built-in sum and difference
circuits, and the gain for these servo signals can be
adjusted using serial interface controls. Each of the
signals from the photodiodes, used to generate DPD
(Differential Phase Detection) tracking servo signal,
is current-to-voltage converted and then also output.
It operates from a single 5 V supply, and is available
in 36-pin plastic SSOP packages.
FEATURES
s RAM/ROM gain switching, low-noise RF signal
generator (differential output)
s ROM tracking DPD signal output
s Variable-gain RAM tracking push-pull signal out-
put
s Address signal, high-speed push-pull signal output
s Variable-gain focus error signal output
s Tracking PD sum signal output
s Focus PD sum signal output
s Offset correction timing output (logic)
s Temperature monitor function
s Serial interface to control internal parameter set-
tings
s Sleep-mode function
s Single 5 V supply
s 36-pin plastic SSOP
PINOUT
36-pin SSOP
(Top view)
MODE 1
WRITE 2
DGND 3
DVCC 4
TEMPO 5
TEMPI 6
T1 7
T2 8
T3 9
T4 10
F1 11
F2 12
AGND 13
VREF 14
FSUBB 15
FSUB 16
FADDB 17
FADD 18
TYPICAL APPLICATIONS
s Double-speed DVDROM equipment
s Double-speed DVDRAM equipment
ORDERING INFORMATION
Device
SM9103M
Package
36-pin SSOP
36 SCLK
35 SDATA
34 SENB
33 CALREQ
32 TADD
31 TADDB
30 CAPAP
29 CAPAN
28 TSUB
27 TSUBB
26 DATAP
25 DATAN
24 DPDA
23 DPDB
22 DPDC
21 DPDD
20 AVCC
19 AGND
NIPPON PRECISION CIRCUITS—1
1 page  
SM9103M
DC Electrical Characteristics
VCC = 5 V ± 5%, GND = 0 V, Ta = 0 to 70 °C
Parameter
Symbol
Condition
Rating
min typ
Current consumption1
ICC1 Operating mode
ICC2 Sleep mode
–
–
MODE, WRITE, SENB, SDATA, SCLK HIGH-level
input voltage
VIH
0.8VCC
24
–
–
MODE, WRITE, SENB, SDATA, SCLK LOW-level
input voltage
VIL
––
MODE, WRITE HIGH-level input current
IIH1 VIN = VCC
SENB, SDATA, SCLK HIGH-level input current
IIH2 VIN = VCC
MODE, WRITE, SENB, SDATA, SCLK LOW-level
input current
IIL
VIN = 0 V
50 100
––
−3 –
CALREQ HIGH-level output voltage
CALREQ LOW-level output voltage
SDATA LOW-level output voltage
VREF input current
VOH
VOL1
VOL2
IREF
IOH = −0.2 mA
IOL = 0.8 mA
IOL = 7 mA
VREF = 2.0 V
VCC − 0.2
–
–
–
–
–
–
–
1. 18 kΩ resistor connected between TSUB and TSUBB
47 kΩ resistor connected between TADD and TADDB
22 kΩ resistor connected between FSUB and FSUBB
27 kΩ resistor connected between FADD and FADDB
SENB, SDATA, SCLK connected to GND; All other pins (excluding supply and ground pins) open circuit.
Tracking PD Input Characteristics (T1, T2, T3, T4)
VCC = 5 V ± 5%, GND = 0 V, Ta = 0 to 70 °C
Parameter
Condition
min
Input impedance
Input conversion noise current
No signal
100 kHz to 10 MHz
RAM read1
ROM read1
–
–
–
Pin voltage
No signal
–
1. DATAP − DATAN output difference operation when 10 pF capacitors are connected to T1, T2, T3, T4
Rating
typ
–
0.035
0.27
–
max
30
1
–
0.2VCC
200
3
–
–
0.4
1.0
250
max
250
–
–
1.5
Unit
mA
V
V
µA
µA
µA
V
V
V
µA
Unit
Ω
µArms
V
NIPPON PRECISION CIRCUITS—5
5 Page 
SM9103M
FUNCTIONAL DESCRIPTION
Serial Interface
The SM9103M uses a serial interface comprising 2
ports to control and set TSUB/FSUB output gain
switching, sleep mode to reduce current consump-
Table 1. Port address and bit configuration1
tion, and TSUB/FSUB offset correction. The address
and bit configuration of each port is shown in table 1.
Bit number
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Data Address
MSB LSB
TG3 TG2 TG1 TG0 FG3 FG2 FG1 FG0 × LOW LOW LOW LOW LOW ×
×
SL1 CS1 – – – – – – × LOW LOW LOW LOW HIGH × ×
1. × = don’t care, – = unassigned
TG3 to TG0: TSUB gain set bits. Default = 0111 (0 dB)
FG3 to FG0: FSUB gain set bits. Default = 0111 (0 dB)
SL1: sleep mode set bit. Sleep mode when 1, normal operation when 0. Default = 0.
CS1: offset correction control. Offset correction when 1, normal operation when 0. Default = 0.
Serial data is input on SDATA with the LSB first in
sync with the falling edge of the SCLK clock. After
the 16th SCLK falling edge and 16 bits of valid data
has been input, the SDATA n-channel open-drain
output goes LOW to perform the function of an
acknowledge signal.
If the number of SCLK cycles which occur when
SENB (serial interface enable) is HIGH is less than
16, the received data is ignored and the internal port
is not updated. If the number of SCLK cycles is
greater than 16, the data is still considered value up
to the 16th SCLK falling edge, the data is latched
into the internal port, and the acknowledge signal is
output. The acknowledge signal is held until SENB
goes LOW again.
Data Signal Processor
This stage creates the data signal and ID signal for
output. The weak current from the tracking PD cells
(T1, T2, T3, T4) are input to the front-end amplifier
where the signals are current-to-voltage converted at
fixed gain.
The gain setting is controlled by pins WRITE and
MODE. WRITE switches between read/write, and
MODE switches the gain between values corre-
sponding to high-reflectivity and low-reflectivity
discs. These signals control the settings for RAM
(low-reflectivity disc) read/write and ROM
(high-reflectivity disc) read.
The front-end amplifier outputs are processed by the
signal processor block to generate intermediate sig-
nals. The data signal, (A + B + C + D), is converted
to a difference signal by a differential output buffer
and output on DATAP and DATAN. The ID signal,
generated from the difference between 2 signals, (A
+ B) and (C + D), is converted to a difference signal
by a differential output buffer and output on CAPAP
and CAPAN. The data signal (DATAP, DATAN) and
ID signal (CAPAP, CAPAN) DC components are
removed using output stage capacitive networks.
T1, T2, T3 and T4 have a hold function to provide
the appropriate reverse bias required by the tracking
PD to ensure the data read bandwidth.
NIPPON PRECISION CIRCUITS—11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet SM9103M.PDF ] | |
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