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PDF MC74HC4060A Data sheet ( Hoja de datos )
| Número de pieza | MC74HC4060A | |
| Descripción | 14-Stage Binary Ripple Counter | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC74HC4060A
14-Stage Binary Ripple
Counter With Oscillator
High−Performance Silicon−Gate CMOS
The MC74HC4060A is identical in pinout to the standard CMOS
MC14060B. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
This device consists of 14 master−slave flip−flops and an oscillator
with a frequency that is controlled either by a crystal or by an RC
circuit connected externally. The output of each flip−flop feeds the
next and the frequency at each output is half of that of the preceding
one. The state of the counter advances on the negative−going edge of
the Osc In. The active−high Reset is asynchronous and disables the
oscillator to allow very low power consumption during stand−by
operation.
State changes of the Q outputs do not occur simultaneously because
of internal ripple delays. Therefore, decoded output signals are subject
to decoding spikes and may have to be gated with Osc Out 2 of the
HC4060A.
Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With JEDEC Standard No. 7A Requirements
• Chip Complexity: 390 FETs or 97.5 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
LOGIC DIAGRAM
Osc Out 1 Osc Out 2
10 9
Osc In 11
Reset 12
7 Q4
5 Q5
4 Q6
6 Q7
14 Q8
13 Q9
15 Q10
1 Q12
2 Q13
3 Q14
Pin 16 = VCC
Pin 8 = GND
© Semiconductor Components Industries, LLC, 2016
June, 2016 − Rev. 10
1
www.onsemi.com
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
PIN ASSIGNMENT
VCC Q10 Q8
16 15 14
Osc Osc
Q9 Reset Osc In Out 1 Out 2
13 12 11 10 9
12345678
Q12 Q13 Q14 Q6 Q5 Q7 Q4 GND
16−Lead Package (Top View)
MARKING DIAGRAMS
16
HC4060AG
AWLYWW
1
SOIC−16
16
HC40
60A
ALYWG
G
1
TSSOP−16
A
L, WL
Y, YY
W, WW
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
Clock
X
FUNCTION TABLE
Reset
L
L
H
Output State
No Change
Advance to Next State
All Outputs Are Low
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Publication Order Number:
MC74HC4060A/D
1 page  
MC74HC4060A
PIN DESCRIPTIONS
INPUTS
Osc In (Pin 11)
Negative−edge triggering clock input. A high−to−low
transition on this input advances the state of the counter. Osc
In may be driven by an external clock source.
Reset (Pin 12)
Active−high reset. A high level applied to this input
asynchronously resets the counter to its zero state (forcing
all Q outputs low) and disables the oscillator.
OUTPUTS
Q4—Q10, Q12−Q14 (Pins 7, 5, 4, 6, 13, 15, 1, 2, 3)
Active−high outputs. Each Qn output divides the Clock
input frequency by 2N. The user should note the Q1, Q2, Q3
and Q11 are not available as outputs.
Osc Out 1, Osc Out 2 (Pins 9, 10)
Oscillator outputs. These pins are used in conjunction
with Osc In and the external components to form an
oscillator. When Osc In is being driven with an external
clock source, Osc Out 1 and Osc Out 2 must be left open
circuited. With the crystal oscillator configuration in
Figure 6, Osc Out 2 must be left open circuited.
SWITCHING WAVEFORMS
tf tr
Osc In
Q
90%
50%
10%
tw
90%
50%
10%
tPLH
tTLH
1/fMAX
tPHL
tTHL
Figure 1.
VCC
GND
Reset
Q
tw
50%
tPHL
50%
Osc In
Figure 2.
VCC
GND
trec
50%
VCC
GND
Qn
Qn+1
50%
tPLH
50%
tPHL
Figure 3.
VCC
GND
DEVICE
UNDER
TEST
TEST
POINT
OUTPUT
CL*
*Includes all probe and jig capacitance
Figure 4. Test Circuit
www.onsemi.com
5
5 Page 
MC74HC4060A
PACKAGE DIMENSIONS
−A−
16
1
SOIC−16
CASE 751B−05
ISSUE K
9
−B− P 8 PL
8 0.25 (0.010) M B S
−T− SEATING
PLANE
G
K
C
D 16 PL
0.25 (0.010) M T B S A S
R X 45_
F
MJ
SOLDERING FOOTPRINT*
8X
6.40
16X 1.12
1 16
16X
0.58
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC
0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
1.27
PITCH
89
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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11
MC74HC4060A/D
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet MC74HC4060A.PDF ] | |
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