|
|
PDF IS61LV12816 Data sheet ( Hoja de datos )
| Número de pieza | IS61LV12816 | |
| Descripción | 128K x 16 HIGH-SPEED CMOS STATIC RAM | |
| Fabricantes | ISSI | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de IS61LV12816 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
|
No Preview Available !
IS61LV12816
128K x 16 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY
ISSI®
FEBRUARY 2003
FEATURES
• High-speed access time: 10, 12, and 15 ns
• CMOS low power operation
• TTL and CMOS compatible interface levels
• Single 3.3V ± 10% power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
DESCRIPTION
The ISSI IS61LV12816 is a high-speed, 2,097,152-bit static
RAM organized as 131,072 words by 16 bits. It is fabricated
using ISSI's high-performance CMOS technology. This
highly reliable process coupled with innovative circuit design
techniques, yields access times as fast as 10 ns with low
power consumption.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS61LV12816 is packaged in the JEDEC standard 44-
pin 400-mil SOJ, 44-pin TSOP (Type II), 44-pin LQFP, and
48-pin mini BGA (6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
www.DataSheet4U.com
A0-A16
DECODER
128K x 16
MEMORY ARRAY
VDD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE
OE CONTROL
WE CIRCUIT
UB
LB
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
02/05/2003
1
1 page  
IS61LV12816
CAPACITANCE(1)
Symbol Parameter
Conditions
Max.
Unit
CIN Input Capacitance
VIN = 0V
6 pF
COUT
Input/Output Capacitance
VOUT = 0V
8 pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
ISSI ®
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-10 ns
-12 ns
-15 ns
Symbol Parameter
Min. Max. Min. Max. Min. Max.
Unit
tRC Read Cycle Time
10 — 12 — 15 —
ns
tAA Address Access Time
— 10 — 12 — 15
ns
tOHA Output Hold Time
3—
3—
3—
ns
tACE CE Access Time
— 10 — 12 — 15
ns
tDOE OE Access Time
—4 —5 — 6
ns
tHZOE(2) OE to High-Z Output
—4
—5
0
6
ns
tLZOE(2) OE to Low-Z Output
0— 0— 0 —
ns
tHZCE(2) CE to High-Z Output
04 05 0 8
ns
tLZCE(2) CE to Low-Z Output
3— 3— 3 —
ns
tBA LB, UB Access Time
—4 —5 — 6
ns
tHZB(2) LB, UB to High-Z Output 0 4 0 5 0 6
ns
tLZB(2) LB, UB to Low-Z Output
0— 0— 0 —
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input
pulse levels of 0V to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not
100% tested.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
02/05/2003
5
5 Page 
IS61LV12816
WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3)
t WC
t WC
ADDRESS
ADDRESS 1
ADDRESS 2
ISSI ®
OE
CE LOW
t SA
WE
UB, LB
DOUT
DIN
t PBW
t HZWE
DATA UNDEFINED
WORD 1
HIGH-Z
t SD
DATAIN
VALID
t HA
t SA
t PBW
WORD 2
t HA
t LZWE
t HD
t SD
DATAIN
VALID
t HD
UB_CEWR4.eps
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is
referenced to the rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
02/05/2003
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet IS61LV12816.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| IS61LV12816 | 128K x 16 HIGH-SPEED CMOS STATIC RAM |  Integrated Circuit Solution |
| IS61LV12816 | 128K x 16 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY |  Integrated Silicon Solution |
| IS61LV12816 | 128K x 16 HIGH-SPEED CMOS STATIC RAM | ISSI |
| IS61LV12816L | 128K x 16 HIGH-SPEED CMOS STATIC RAM | Integrated Silicon Solution |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |