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PDF LR38666Y Data sheet ( Hoja de datos )
| Número de pieza | LR38666Y | |
| Descripción | CMOS digital signal processor | |
| Fabricantes | Sharp Electrionic | |
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LR38666Y
LR38666Y
DESCRIPTION
The LR38666Y is a CMOS digital signal processor
for color digital still camera systems of 1 310 k/ 2 140 k/
3 300 k/3 370 k/4 200 k-pixel CCDs with primary
color mosaic filters.
One-chip System LSI for Digital Still
Cameras
• Power supplies
– +2.5 V for digital/analog circuits
– +3.3 V for digital circuits
• Package : 240-ball CSP (T-TFBGA240-1414)
FEATURES
• ARM7TDMI is used as the CPU core
• CCD signal processor modules
– Supported image size : 1 310 k/ 2 140 k/3 300 k/
3 370 k/4 200 k pixels
– R, G and B primary color mosaic filters :
Bayer matrix, 10 bits per color
– Built-in auto focus, auto exposure and auto
white balance functions
– Built-in digital clamp and gamma correction
functions
• Video encoder module
– Composite analog signal output mode : www.DataSheet4U.com
Switchable between NTSC and PAL
– Built-in OSDC function
• JPEG encoding/decoding module :
Built-in circuits for encoding and decoding
– Encoding rate : Max. 66 ms per frame
(for 1/10-compression in VGA mode)
– Decoding rate : Max. 66 ms per frame
(for decompression in VGA mode)
(Assuming that SDRAM is used and the internal
bus is occupied by the JPEG module)
• SDRAM/flash memory controller module
• Synchronous/asynchronous SIO
• USB 1.0 is supported
• General purpose I/O ports
• Built-in audio I/F
• Built-in resizing function
• Built-in CompactFlash I/F
• Built-in SmartMedia I/F
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in
catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
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1 page  
LR38666Y
PIN NO. COORDINATE SYMBOL
40 5K DGND
41 1K MEMD20
42 6L TEST4Z
43 5L TEST5Z
44 2L DVDD
45 1L MEMD21
46 3L MEMD22
47 1M MEMD23
48 4L DGND
49 4M MEMD24
50 2M DVDD2
51 3M MEMD25
52 1N MEMD26
53 4N MEMD27
54 2N DGND
55 3N MEMD28
56 1P DVDD
57 1R MEMD29
58 3P MEMD30
59 2P MEMD31
60 – NC
61 2R DGND
62 3R MEMLDQM
63 2T MEMUDQM
64 4P MEMRASZ
65 4R MEMCASZ
66 3T DVDD
67 5P DGND
68 4T MEMCLK
69 5R DVDD2
70 5N MEMWEZ
71 5M MEMA0
72 6N MEMA1
73 6P DGND
74 5T MEMA2
75 6R DVDD
76 6M MEMA3
77 7M MEMA4
78 6T MEMA5
79 7N DGND
IO SYMBOL
DESCRIPTION
– Ground
IO12U Data I/O for SDRAM/external device/GIO20
IU
Test (Must be open.)
IU
– Power supply (+3.3 V)
IO12U Data I/O for SDRAM/external device/GIO21
IO12U Data I/O for SDRAM/external device/GIO22
IO12U Data I/O for SDRAM/external device/GIO23
– Ground
IO12U Data I/O for SDRAM/external device/GIO24
– Internal power supply (+2.5 V)
IO12U Data I/O for SDRAM/external device/GIO25
IO12U Data I/O for SDRAM/external device/GIO26
IO12U Data I/O for SDRAM/external device/GIO27
– Ground
IO12U Data I/O for SDRAM/external device/GIO28
– Power supply (+3.3 V)
IO12U Data I/O for SDRAM/external device/GIO29
IO12U Data I/O for SDRAM/external device/GIO30
IO12U Data I/O for SDRAM/external device/GIO31
– Must be open.
– Ground
16-bit data mode : Control MEMD7-MEMD0 of SDRAM
O12
32-bit data mode : Control MEMD23-MEMD16 of SDRAM
16-bit data mode : Control MEMD15-MEMD8 of SDRAM
O12
32-bit data mode : Control MEMD31-MEMD24 of SDRAM
O12 SDRAM row address strobe
O12 SDRAM column address strobe
– Power supply (+3.3 V)
– Ground
IO12 SDRAM clock output (49.0908 MHz : double of C24MI input)
– Internal power supply (+2.5 V)
O12 SDRAM write enable
O12
Address for SDRAM/flash memory/external device
O12
– Ground
O12 Address for SDRAM/flash memory/external device
– Power supply (+3.3 V)
O12 Address for SDRAM/flash memory/external device
O12 Address for SDRAM/flash memory/external device
O12 Address for SDRAM/flash memory/external device
– Ground
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5 Page 
FUNCTIONAL DESCRIPTION
Oscillation Circuit
The PLL included in the LR38666Y divides or
LR38666Y
passes through the doubled frequency of the quartz
crystal connected to I/O pins, and provides it to the
internal logic circuits as shown in Fig.1 and Fig.2.
C24MI (or C29MI or COMI)
Oscillation Circuit
(PLL)
Frequency
Divider
C24MO
(or C29MO or COMO)
Fig. 1 Block Diagram of Oscillation Circuit
To Internal Logic
C1 C24MI
(or C29MI or COMI)
RD2
C2 RD1
C24MO
(or C29MO or COMO)
Fig. 2 Clock Input to Oscillation Circuit
Connection of Quartz Crystal (TA = 0 to +70˚C) : Example of Oscillation under Fundamental Frequencies
APPLICABLE PINS
C24MI, C24MO
C29MI, C29MO
COMI, COMO
FUNDAMENTAL
FREQUENCY [MHz]
24.5454
29.5000
24.0000
C1 [pF]
10
10
10
RECOMMENDED COEFFICIENT
C2 [pF]
RD1 [$]
10 220
10 220
10 220
RD2 [$]
1M
1M
1M
NOTES :
1. The oscillation circuit should be located as close to C24MI, C24MO (C29MI, C29MO, COMI, COMO) as possible.
2. Do not install other signal lines in the shaded area.
3. Perform due evaluation on the match between the LR38666Y and the quartz crystal.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LR38666Y.PDF ] | |
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