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PDF MWS5101 Data sheet ( Hoja de datos )
| Número de pieza | MWS5101 | |
| Descripción | 256-Word x 4-Bit LSI Static RAM | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MWS5101 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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March 1997
MWS5101,
MWS5101A
256-Word x 4-Bit
LSI Static RAM
Features
Description
• Industry Standard Pinout
• Very Low Operating Current . . . . . . . . . . . . . . . . . . 8mA
at VDD = 5V and Cycle Time = 1µs
• Two Chip Select Inputs Simple Memory Expansion
• Memory Retention for Standby. . . . . . . . . . . . . 2V (Min)
Battery Voltage
• Output Disable for Common I/O Systems
• Three-State Data Output for Bus Oriented Systems
• Separate Data Inputs and Outputs
• TTL Compatible (MWS5101A)
Pinout
MWS5101, MWS5101A
(PDIP, SBDIP)
TOP VIEW
A3 1
A2 2
A1 3
A0 4
A5 5
A6 6
A7 7
VSS 8
DI1 9
DO1 10
DI2 11
22 VDD
21 A4
20 R/W
19 CSI
18 O.D.
17 CS2
16 DO4
15 DI4
14 DO3
13 DI3
12 DO2
The MWS5101 and MWS5101A are 256 word by 4-bit static
random access memories designed for use in memory
systems where high speed, very low operating current, and
simplicity in use are desirable. They have separate data
inputs and outputs and utilize a single power supply of 4V to
6.5V. The MWS5101 and MWS5101A differ in input voltage
characteristics (MWS5101A is TTL compatible).
Two Chip Select inputs are provided to simplify system
expansion. An Output Disable control provides Wire-OR
capability and is also useful in common Input/Output
systems by forcing the output into a high impedance state
during a write operation independent of the Chip Select input
condition. The output assumes a high impedance state
when the Output Disable is at high level or when the chip is
deselected by CS1 and/or CS2.
The high noise immunity of the CMOS technology is
preserved in this design. For TTL interfacing at 5V operation,
excellent system noise margin is preserved by using an
external pull-up resistor at each input.
For applications requiring wider temperature and operating
voltage ranges, the mechanically and functionally equivalent
static RAM, CDP1822 may be used.
The MWS5101 and MWS5101A types are supplied in 22
lead hermetic dual-in-line, sidebrazed ceramic packages (D
suffix), in 22 lead dual-in-line plastic packages (E suffix), and
in chip form (H suffix).
Ordering Information
PACKAGE
PDIP
Burn-In
SBDIP
Burn-In
TEMP. RANGE
0oC to +70oC
0oC to +70oC
MWS5101
250ns
MWS5101EL2
-
MWS5101A
350ns
250ns
350ns
PKG. NO.
MWS5101ELS MWS5101AEL2 MWS5101AEL3 E22.4
MWS5101AEL3X E22.4
MWS5101DL3X
- MWS5101ADL3 D22.4A
D22.4A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-56
File Number 1106.2
1 page  
MWS5101, MWS5101A
A0 - A7
CHIP SELECT 1
CHIP SELECT 2
OUTPUT DISABLE
READ/WRITE
DATA OUT
tRC
tDOA1
tDOA2
tDOA3
tDOH1
tDOH2
tDOH3
tAA
HIGH
IMPEDANCE
DATA OUT
VALID
FIGURE 1. READ CYCLE TIMING WAVEFORMS
HIGH
IMPEDANCE
A0-A7
CHIP SELECT 1
tCS1S
tWC
tWR
tCS1H
CHIP SELECT 2
OUTPUT DISABLE
DI1-DI4
(NOTE)
tODS
tCS2S
tCS2H
tDS
DATA IN STABLE
tDH
READ/WRITE
tWRW
tAS
DON’T CARE
NOTE: tODS is required for common I/O operation only; for separate I/O operations, output disable is “don’t care”.
FIGURE 2. WRITE CYCLE TIME WAVEFORMS
6-60
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet MWS5101.PDF ] | |
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