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PDF ISL6173 Data sheet ( Hoja de datos )
| Número de pieza | ISL6173 | |
| Descripción | Dual Low Voltage Hot Swap Controller | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
January 3, 2006
ISL6173
FN9186.3
Dual Low Voltage Hot Swap Controller
This IC targets dual voltage hot swap applications across the
+2.5V to +3.3V (nominal) bias supply voltage range with a
second lower voltage rail down to less than 1V. It features a
charge pump for driving external N-Channel MOSFETs,
regulated current protection and duration, output undervoltage
monitoring and reporting, optional latch-off or retry response,
and adjustable soft-start.
The current regulation level (CR) for each rail is set by two
external resistors and each CR duration is set by an external
capacitor on the TIM pin. After the CR duration has expired
the IC then quickly pulls down the associated GATE(s)
output turning off its external FET(s). The ISL6173 offers a
latched output or indefinite auto retry mode of operation.
Ordering Information
PART NUMBER
(Note)
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL6173DRZA ISL6173DRZ 0 to +85 28 Ld 5x5 QFN L28.5x5
ISL6173DRZA-T ISL6173DRZ 0 to +85 28 Ld 5x5 QFN L28.5x5
Tape & Reel
ISL6173EVAL3 Evaluation Platform
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Pinout
ISL6173 (28 LD QFN) TOP VIEW
Features
• Fast Current Regulation amplifier quickly responds to
overcurrent fault conditions
• Less than 1µs response Time to Dead Short
• Programmable Current Regulation Level and Duration
• Two Levels of Overcurrent Detection Provide Fast
Response to Varying Fault Conditions
• Overcurrent Circuit Breaker and Fault Isolation functions
• Adjustable Current Regulation Threshold as low as 20mV
• Selectable Latch-off or Auto Retry Response to Fault
conditions
• Adjustable voltage ramp-up for In-rush Protection During
Turn-On
• Rail Independent Control, Monitoring and Reporting I/O
• Dual Supply Hot Swap Power Distribution Control to <1V
• Charge Pump Allows the use of N-Channel MOSFETs
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Power Supply Sequencing, Distribution and Control
• Hot Swap/Electronic Breaker Circuits
V1(in)
Rsns1
V1(out)
28 27 26 25 24 23 22
SNS1 1
21 SNS2
VO1 2
20 VO2
SS1 3
19 SS2
GT1 4
18 GT2
FLT1 5
17 FLT2
PG1 6
16 PG2
CT1 7
15 CT2
8 9 10 11 12 13 14
EN1 EN2
RTR/LTCH
BIAS
CPQ+
VS1
SNS1
GT1 VO1
UV1
PG1
FLT1
SS1
CPQ-
CPVDD
ISL6173
OCREF
SS2
FLT2
PGND
PG2
GND
UV2
CT1 CT2 VS2 SNS2 GT2 VO2
V2(in)
Rsns2
FIGURE 1. TYPICAL APPLICATION
V2(OUT)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6173
Absolute Maximum Ratings
VBIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V
GTx, CPQ+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +12V
ENx, RTR/LTCH, SNSx, PGx, FLTx, VSx, CTx, UVx,
SSx, CPQ-, CPVDD. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.5VDC
Output Current . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protected
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . .1750V
Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . .125V
Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . .1750V
Thermal Information
Thermal Resistance (Typical, Notes 1, 4) θJA (°C/W) θJC (°C/W)
5x5 QFN Package . . . . . . . . . . . . . . . .
42
12.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
For recommended soldering conditions, see Tech Brief TB389.
(QFN - Leads Only)
Operating Conditions
VBIAS/VIN1 Supply Voltage Range. . . . . . . . . . . . +2.25V to +3.63V
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. All voltages are relative to GND, unless otherwise specified.
3. 1V (min) on the BIAS pin required for FLT to be valid.
4. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications VDD = 2.5V to +3.3V, VS = 1V ,TA = TJ = 0°C - 85°C, Unless Otherwise Specified.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP
CURRENT REGULATION CONTROL
ISET Current
Partial Temp Range ISET Current
Current Limit Amp Offset Voltage
Partial Temp. Current Limit Amp Offset
Voltage
Current Regulation Threshold Voltage
Current Regulation Accuracy
Current Regulation Threshold Voltage
Current Regulation Accuracy
Current Regulation Threshold Voltage
Current Regulation Accuracy
CT Threshold Voltage
CT Charging Current
GATE DRIVE
ISET_ft
ISET_pt
Vio_ft
Vio_pt
VCRVTH_1
VCRVTH_1R
VCRVTH_2
VCRVTH_2R
VCRVTH_3
VCRVTH_3R
VCT_Vth
ICT
ROCREF = 14.7kΩ
RTJO=CR2E5oFC=
14.7kΩ
to 60oC
VVS - VSNS with IOUT = 0A
VVS - VSNS with IOUT = 0A
TJ = 25°C to 60°C
RISET = 1.25K, ISET = 20µA
RISET = 1.25K, ISET = 20µA
RISET = 2.50K, ISET = 20µA
RISET = 2.50K, ISET = 20µA
RISET = 0.499K, ISET = 20µA
RISET = 0.499K, ISET = 20µA
18.7
19
-2
-1
23
-8
48
-4
8
-20
1.128
20
20
25
50
10
1.178
10
GATE Response Time from WOC (Open)
pd_woc_open
GATE open
100mV of overdrive on the WOC
comparator
3
GATE Response Time from WOC
(Loaded)
pd_woc_load GATE = 1nF
100
GATE Response Time in Current
Regulation mode (Loaded)
pd_cr_load
GATE = 1nF
120% Load Current
5
GATE Turn-On Current
IGATE
GATE = 2V, VVS = 2V, VSNS = 2.1V
21
24
MAX
UNIT
21.3
21
2
1
27
+8
52
+4
12
+20
1.202
µA
µA
mV
mV
mV
%
mV
%
mV
%
V
µA
ns
ns
µs
27 µA
5 FN9186.3
January 3, 2006
5 Page 
ISL6173
The two channels can be forced to track each other by
simply tying their SS pins together and using a common SS
capacitor. In addition, their EN pins also must be tied
together. Typical Start-up waveforms in this mode are shown
in Figure 15. If one channel goes down for any reason, the
other one will too. One important thing to note here is that
only the overcurrent latch-off mode will work. Auto-retry
feature WILL NOT work. Retry must be controlled manually
through EN.
Typical Hot-plug Power Up Sequence
1. When power is applied to the IC on the BIAS pin, the first
charge pump immediately powers up.
2. If the BIAS voltage is 2.1V or higher, the IC comes out of
POR. Both SS and CT caps remain discharged and the
gate (GT) voltage remains low.
3. ENx pin, when pulled low (below it’s specified threshold),
enables the respective channel.
4. SSx cap begins to charge up through the internal 10µA
current source, the gate (GT) voltage begins to rise and
the corresponding output voltage begins to rise at the
same rate as the SS cap voltage. This is tightly controlled
by the soft-start amplifier shown in the block diagram.
5. SS cap begins to charge but the corresponding CTx cap
is held discharged.
6. Fault (FLT) remains deasserted (stays high) and the
output voltage continues to rise.
7. If the load current on the output exceeds the set current
limit for greater than the OC timeout period, FLT gets
asserted and the channel shutdown occurs.
8. If the voltage on UV pin exceeds 633mV threshold as a
result of rising Vo, the Power Good (PG) output goes
active.
9. At the end of the SS interval, the SS cap voltage reaches
CPVDD and remains charged as long as EN remains
asserted or there is no other fault condition present that
would attempt to pull down the gate.
State Diagram
This is shown in Figure 16. It provides a quick overview of
the IC operation and can also be used as a troubleshooting
road map.
11 FN9186.3
January 3, 2006
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ISL6173.PDF ] | |
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