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PDF AT24C256B Data sheet ( Hoja de datos )
| Número de pieza | AT24C256B | |
| Descripción | Two-wire Serial EEPROM 256K | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Low-voltage and Standard-voltage Operation
– 1.8 (VCC = 1.8V to 5.5V)
• Internally Organized as 32,768 x 8
• Two-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 1 MHz (5.0V, 2.7V, 2.5V), and 400 kHz (1.8V) Compatibility
• Write Protect Pin for Hardware and Software Data Protection
• 64-byte Page Write Mode (Partial Page Writes Allowed)
• Self-timed Write Cycle (5 ms Max)
• High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 40 Years
• Lead-free/Halogen-free Devices Available
• 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, EIAJ SOIC, 8-lead Ultra Thin Small Array
Package (SAP), 8-lead TSSOP, and 8-ball dBGA2 Packages
• Die Sales: Wafer Form, Waffle Pack and Bumped Wafers
Two-wire Serial
EEPROM
256K (32,768 x 8)
AT24C256B
Description
The AT24C256B provides 262,144 bits of serial electrically erasable and programma-
ble read-only memory (EEPROM) organized as 32,768 words of 8 bits each. The
device’s cascadable feature allows up to eight devices to share a common two-wire
bus. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The devices are available
in space-saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin SAP, 8-
lead TSSOP, and 8-ball dBGA2 packages. In addition, the entire family is available in
a 1.8V (1.8V to 5.5V) version.
Not
Recommended
for New Design
Pin Configurations
8-lead PDIP
8-lead SOIC
Pin Name
A0–A2
SDA
SCL
WP
GND
Function
Address Inputs
Serial Data
Serial Clock Input
Write Protect
Ground
A0
A1
A2
GND
1
2
3
4
8 VCC
A0
7 WP
A1
6 SCL
A2
5 SDA GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
8-lead dBGA2
VCC 8
WP 7
SCL 6
SDA 5
1 A0
2 A1
3 A2
4 GND
8-lead TSSOP
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
Bottom View
8-lead Ultra Thin SAP
VCC 8
WP 7
SCL 6
SDA 5
1 A0
2 A1
3 A2
4 GND
Bottom View
Rev. 5279C–SEEPR–3/09
1 page  
AT24C256B
Table 3-3. AC Characteristics (Industrial Temperature)
Applicable over recommended operating range from TAI = 40C to +85C, VCC = +1.8V to +5.5V, CL = 100 pF (unless oth-
erwise noted). Test conditions are listed in Note 2.
1.8-volt
2.5, 5.0-volt
Symbol
Parameter
Min Max Min Max Units
fSCL
tLOW
tHIGH
ti
tAA
tBUF
Clock Frequency, SCL
400 1000
Clock Pulse Width Low
1.3
0.4
Clock Pulse Width High
0.6
0.4
Noise Suppression Time(1)
100 50
Clock Low to Data Out Valid
0.05 0.9 0.05 0.55
Time the bus must be free before a
new transmission can start(1)
1.3
0.5
kHz
µs
µs
ns
µs
µs
tHD.STA
Start Hold Time
0.6 0.25
µs
tSU.STA
Start Set-up Time
0.6 0.25
µs
tHD.DAT
Data In Hold Time
00
µs
tSU.DAT
tR
tF
Data In Set-up Time
Inputs Rise Time(1)
Inputs Fall Time(1)
100 100
0.3 0.3
300 100
ns
µs
ns
tSU.STO
Stop Set-up Time
0.6 0.25
µs
tDH Data Out Hold Time
50 50
ns
tWR Write Cycle Time
5 5 ms
Endurance(1) 25°C, Page Mode, 3.3V
1,000,000
Write
Cycles
Notes: 1. This parameter is ensured by characterization and is not 100% tested.
2. AC measurement conditions:
RL (connects to VCC): 1.3 k (2.5V, 5.5V), 10 k (1.8V)
Input pulse voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: 50 ns
Input and output timing reference voltages: 0.5 VCC
5279C–SEEPR–3/09
5
5 Page 
AT24C256B
7. Read Operations
Read operations are initiated the same way as write operations with the exception that the
read/write select bit in the device address word is set to “1”. There are three read operations:
current address read, random address read, and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last
address accessed during the last read or write operation, incremented by one. This address
stays valid between operations as long as the chip power is maintained. The address “roll over”
during read is from the last byte of the last memory page, to the first byte of the first page.
Once the device address with the read/write select bit set to “1” is clocked in and acknowledged
by the EEPROM, the current address data word is serially clocked out. The microcontroller does
not respond with an input “0” but does generate a following stop condition (see Figure 7-1).
Figure 7-1. Current Address Read
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data
word address. Once the device address word and data word address are clocked in and
acknowledged by the EEPROM, the microcontroller must generate another start condition. The
microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks
out the data word. The microcontroller does not respond with a “0” but does generate a following
stop condition (see Figure 7-2).
Figure 7-2. Random Read
Note: * = DON’T CARE bit
5279C–SEEPR–3/09
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet AT24C256B.PDF ] | |
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