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PDF AT24C64C Data sheet ( Hoja de datos )
| Número de pieza | AT24C64C | |
| Descripción | 2-Wire Serial EEPROM | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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(Features
• Low-voltage and Standard-voltage Operation
– 1.8 (VCC = 1.8 to 5.5V)
• Internally Organized 4096 x 8, 8192 x 8
• 2-Wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bi-directional Data Transfer Protocol
• 1 MHz (5.0V) and 400 KHz (1.8V Compatibility)
• Write Protect Pin for Hardware Data Protection
• 32-Byte Page Write Mode (Partial Page Writes Allowed)
• Self-Timed Write Cycle (5 ms max)
• High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• Lead-free/Halogen-free Devices
• 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Lead Frame Land Grid Array (ULA), 8-lead
TSSOP, 8-lead Ultra Thin Mini-MAP (MLP2x3), and 8-ball dBGA2 Packages.
• Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers
Description
The AT24C32C/64C provides 32,768/65,536 bits of serial electrically erasable and
programmable read only memory (EEPROM) organized as 4096/8192 words of 8 bits
each. The device’s cascadable feature allows up to 8 devices to share a common 2-
wire bus. The device is optimized for use in many industrial and commercial applica-
tions where low power and low voltage operation are essential. The AT24C32C/64C is
available in space saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Lead Frame
Land Grid Array (ULA), 8-lead TSSOP, 8-lead Ultra Thin Mini-MAP (MLP2x3) and, 8-
ball dBGA2 packages and is accessed via a 2-wire serial interface. In addition, the
entire family is available in 1.8V (1.8 to 5.5V) version.
Pin Configurations
8-lead Ultra Thin
8-lead Ultra Lead Frame
Mini-MAP (MLP 2x3) Land Grid Array (ULA)
Pin Name
A0 - A2
SDA
Function
Address Inputs
Serial Data
VCC 8
WP 7
SCL 6
SDA 5
1 A0
2 A1
3 A2
4 GND
VCC 8
WP 7
SCL 6
SDA 5
1 A0
2 A1
3 A2
4 GND
SCL
Serial Clock Input
Bottom View
Bottom View
WP Write Protect
8-ball dBGA2
8-lead TSSOP
VCC 8
WP 7
SCL 6
SDA 5
1 A0
2 A1
3 A2
4 GND
Bottom View
8-lead SOIC
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
8-lead PDIP
A0
A1
A2
GND
1
2
3
4
8 VCC A0 1
7 WP
A1 2
6 SCL A2 3
5 SDA GND 4
8 VCC
7 WP
6 SCL
5 SDA
2-Wire
Serial EEPROM
32K (4096 x 8)
64K (8192 x 8)
AT24C32C
AT24C64C
Not Recommended
for New Design
5298A–SEEPR–1/08
1 page  
AT24C32C/64C
AC Characteristics
Applicable over recommended operating range from TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted)
1.8-volt
5.0-volt
Symbol
Parameter
Min Max Min Max Units
fSCL
tLOW
tHIGH
ti
tAA
tBUF
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time(1)
Clock Low to Data Out Valid
Time the bus must be free before a new
transmission can start(1)
400
1000
kHz
1.3 0.4
µs
0.6 0.4
µs
100 50 ns
0.05 0.9
0.05 0.55
µs
1.3 0.5
µs
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
tF
tSU.STO
tDH
tWR
Endurance(1)
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time(1)
Inputs Fall Time(1)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
25°C, Page Mode, 3.3V
0.6
0.6
0
100
0.3
300
0.6
50
5
0.25
0.25
0
100
0.25
50
1,000,000
µs
µs
µs
ns
0.3 µs
100 ns
µs
ns
5 ms
Write
Cycles
Notes:
1. This parameter is ensured by characterization.
2. AC measurement conditions:
RL (connects to VCC): 1.3 kΩ (2.5V, 5.0V), 10 kΩ (1.8V)
Input pulse voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: ≤ 50 ns
Input and output timing reference voltages: 0.5 VCC
5298A–SEEPR–1/08
5
5 Page 
Figure 12-3. Page Write
t
Note: 1. * = DON’T CARE bits
2. t = DON’T CARE bit for AT24C32C
Figure 12-4. Current Address Read
Figure 12-5. Random Read
Note: 1. * = DON’T CARE bits
5298A–SEEPR–1/08
AT24C32C/64C
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AT24C64C.PDF ] | |
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