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PDF LP62S16512-T Data sheet ( Hoja de datos )
| Número de pieza | LP62S16512-T | |
| Descripción | 512K X 16 BIT LOW VOLTAGE CMOS SRAM | |
| Fabricantes | AMIC Technology | |
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LP62S16512-T Series
Preliminary
512K X 16 BIT LOW VOLTAGE CMOS SRAM
Document Title
512K X 16 BIT LOW VOLTAGE CMOS SRAM
Revision History
Rev. No. History
0.2 Add Product Family and 55ns specification
Issue Date
March 20, 2002
Remark
Preliminary
PRELIMINARY (March, 2002, Version 0.2)
AMIC Technology, Inc.
1 page  
LP62S16512-T Series
Absolute Maximum Ratings*
*Comments
VCC to GND ..............................................-0.5V to +4.0V
IN, IN/OUT Volt to GND ................... -0.5V to VCC + 0.5V
Operating Temperature, Topr ...................-25°C to +85°C
Storage Temperature, Tstg.....................-55°C to +125°C
Power Dissipation, PT ...................................................................... 0.7W
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics (TA = -25°C to + 85°C, VCC = 2.7V to 3.6V, GND = 0V)
Symbol
Parameter
LP62S16512-55/70LLT
Min.
Max.
Unit
Conditions
ILI Input Leakage Current - 1 µA VIN = GND to VCC
ILO Output Leakage Current
Active Power Supply
ICC Current
-
-
CS1 = VIH or CS2 = VIL or
1 µA LB = HB = VIH
VI/O = GND to VCC
CS1 = VIL , CS2 = VIH ,
5 mA
LB = VIL or HB = VIL , II/O = 0mA
ICC1
Dynamic Operating
Current
ICC2
ISB
Standby Current
ISB1
VOL Output Low Voltage
VOH Output High Voltage
Min. Cycle, Duty = 100%, CS1 = VIL ,
- 50 mA
CS2 = VIH , LB = VIL or HB = VIL
II/O = 0mA
CS1 ≤ 0.2V, CS2 ≥ VCC-0.2V ,
- 15 mA LB ≤ 0.2V or HB ≤ 0.2V
f = 1MHz , II/O = 0mA
- 1 mA CS1 = VIH or CS2 = VIL or
LB = HB = VIH
CS1 ≥ VCC - 0.2V or CS2 ≤ 0.2V or
- 20 µA LB = HB ≥ VCC-0.2V
VIN ≥ VCC-0.2V or VIN ≤ 0.2V
- 0.4 V IOL = 2.1 mA
2.2 - V IOH = -1.0 mA
PRELIMINARY (March, 2002, Version 0.2)
4
AMIC Technology, Inc.
5 Page 
Timing Waveforms (continued)
Write Cycle 3
(Byte Enable Controlled)
Address
CS1
CS2
tAS1
LP62S16512-T Series
tWC
tAW
tCW1 , tCW2
tBW2
tWR3
HB, LB
WE
DATA IN
DATA OUT
tWHZ4
tWP
tDW
tDH
tOW
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP, tBW) of a low CS1 , WE and ( HB and , or LB ) or a high CS2.
3. tWR is measured from the earliest of CS1 or WE or ( HB and , or LB ) going high or CS2 going Low to the end of
the Write cycle.
4. OE level is high or low.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY (March, 2002, Version 0.2)
10
AMIC Technology, Inc.
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet LP62S16512-T.PDF ] | |
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