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PDF MP3274 Data sheet ( Hoja de datos )
| Número de pieza | MP3274 | |
| Descripción | 12-Bit Data Acquisition Subsystem | |
| Fabricantes | Exar | |
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FEATURES
• Complete 32-Channel 12-Bit A/D Converter
with Sample & Hold, Reference, Clock and
3-State Outputs
• Fast Conversion, less than 15µS
• Microprocessor Bus Interface
• Parallel or Serial Data Output Modes
• 65 ns Bus Access Time
• Remote Analog Ground Sensing
• Overvoltage Protected Input (50 V over the
Supply Voltages)
MP3274
Fault Protected 32 Channel, 12-Bit
Data Acquisition Subsystem
• Precision Reference for Long Term Stability and
Low Gain T.C.
• Guaranteed Linearity Over Temperature
• Guaranteed Performance at +12/–5 V, ±12 & ±15 V
• Low Power (3 mW per Channel Typical)
• 16 Channel Version: MP3276 & MP3275
GENERAL DESCRIPTION
The MP3274 is a complete 32-channel, 12-bit Data Acquisi-
tion Subsystem with 3-state output buffers for direct interfacing
to 16-bit microprocessor buses. Implemented using an ad-
vanced BiCMOS process, the converter combines a 32-channel
passive overvoltage protected multiplexer instrumentation amp,
a sample & hold, a SAR, a 12-bit decoded D/A, a comparator, a
precision reference and the control logic to achieve an accurate,
repeated conversion in less than 15µs, and a mux/instrumenta-
tion amp settling period of less than 10µs.
A unique input design provides input overvoltage protection
to 50 V over the supply voltages. Therefore, an overvoltage
condition can exist on unselected channels without disrupting
the measured channel or operation of the MP3274! The internal
4 V reference has sufficient output current to provide other sys-
tem reference needs. Precision thin film scaling and offset resis-
tors are laser trimmed to provide for less than 2 LSB INL for +10
V inputs on all channels.
In addition, the MP3274 will output either full scale (0111 ....)
for overrange and – full scale (1000....) for underrange condi-
tions. This greatly simplifies microprocessor software develop-
ment.
SIMPLIFIED BLOCK DIAGRAM
GND REF.
VDD VCC
AB0-4
(5 pins) 5 32 Ch.
AIN0-31
MUX
(32 pins)
32
AGND2
REF IN
REF OUT
4V
REF
AGND3
–
+
REF IN /2
VREF
CLK
Control
Logic
Rev. 4.00
DGND VEE AGND WR RD ADEN STL
CS STS
1
VDAC
12
SAR
12
Latch/
Shift Register
3-State
Drivers
DB0-DB11
AGND
Comp
PXS
1 page  
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MP3274
ELECTRICAL CHARACTERISTICS TABLE (CONT’D)
Description
25°C
Tmin to Tmax
Symbol Min Typ Max Min Max
Units
DIGITAL OUTPUTS
(Data Format 2’s Complement)
DB0/SDC–DB11/SDO, STS, STL
Logical “1” Voltage
Logical “0” Voltage
Tristate Leakage
POWER SUPPLIES
VOH
VOL
IOZ
4.0
–5
2.4 V
0.4 0.4 V
5 –5 5 µA
Operating Range
VDD
VCC
VEE
Operating Current
IDD
ICC
IEE
Power Dissipation
+4.5
+11.4
–4.75
+5.5
+16.5
–16.5
27
58
1.5 3
110 200
+4.5
+11.4
–4.75
+5.5
+16.5
–16.5
V
V
V
7 mA
8 mA
3 mA
200 mW
Conditions
COUT=15 pF
ISOURCE = 0.5 mA
ISINK = 1.6 mA
VOUT=GND to VDD
Tested at –11.4 and –16.5 only
NOTES
1 Tester measures code transitions by dithering the voltage of the analog input (VIN). The difference between the measured and the
ideal code width is the DNL error. The INL error is the maximum distance (in LSBs) from the best fit line to any transition voltage
2 Guaranteed. Not tested.
3 Specified values guarantee functionality. Refer to other parameters for accuracy.
4 Input bandwidth is a measure of performance of the A/D input stage (S/H + amplifier). Refer to other parameters for accuracy
within the specified bandwidth.
5 All channel input pins and ground reference pin have protection which becomes active above 60 V.
6 All digital inputs have diodes to VDD and AGND. Input DC currents will not exceed specified limits for any input voltage between GND
and VDD.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2
VCC to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +16.5 V
VEE to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to –16.5 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +7 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1 V
Digital Inputs/Outputs
to DGND . . . . . . . . . . . . . . . . . . . . . –0.5 V to VLOGIC +0.5 V
Analog Inputs (AIN0 – AIN31, GND REF)
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60 V
REF OUT . . . . . . . . . . . . . . . . . . . Indefinite short to DGND,
Momentary short to VCC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C
Package Power Dissipation Rating to 75°C
PGA, PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1800 mW
Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 25 mW/°C
Lead Temperature, Soldering . . . . . . . . . . . . 300°C, 10 Sec
Storage Temperature (Ceramic) . . . . . . . . –65°C to +150°C
NOTES:
1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps
(HP5082-2835) from input pin to the supplies. All logic inputs have protection diodes which will protect the device from
short transients outside the supplies of less than 100mA for less than 100µs.
Rev. 4.00
5
5 Page 
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MP3274
APPLICATION INFORMATION
The MP3274 is a complete A/D converter system, with its
own built-in reference and clock. It may be used by itself (“stand-
alone” operation), or it may be interfaced with a microprocessor
which can control both conversion and formatting of output.
Successful application of the MP3274 requires careful atten-
tion to four main areas:
1) Physical layout.
2) Connection/Trimming according to mode of operation.
3) Conditioning of input signals.
4) Control and Timing considerations.
Ground Reference
The ground reference pin can be used for remote ground
sensing of a common mode input signal with a maximum 6 V p-p
around AGND.
This common input can also be used to dither each input’s
“zero”. By averaging multiple conversions digitally, higher reso-
lution for each input conversion can be obtained. Patterns for
this dither can be a ramp, a stair step, or white noise.
Physical Layout
The 12-bit accuracy of the MP3274 represents a dynamic
range of 72dB. In order that this be preserved, thorough precau-
tions must be taken to avoid any interfering signals, whether
conducted or radiated.
• Avoid placing the chip and its analog signals near logic
traces. In general, using a double sided printed circuit
card with a good ground plane on the component side is
recommended. Routing analog signals between ground
traces will help isolate digital control logic. If these lines
cross, do so at right angles. The GND Ref. is the positive
terminal of the MUX/Instrumentation amplifier and will
provide common mode noise rejection. It should be
close to and shielded together with the channel inputs in
order to take advantage of this feature.
• Power supplies should be quiet and well regulated.
Grounds should be tied together at the package and
back to the system ground with a single path. Bypass the
supplies at the device with a 0.01 to 0.1µF ceramic cap
and a 10-47 µF tantalum type, in parallel.
“Stand-Alone” Operation
The MP3274 can be used in “stand-alone” operation, which is
useful in systems not requiring full computer bus interface capa-
bility. This operation is available for either parallel or serial mode.
For this operation, CS = 0, ADEN = 1, and conversion is con-
trolled by WR. The 3-state buffers are enabled when RD goes
low. There are two possible conditions that the 3-state buffers
could be in during a conversion. If RD goes low prior to WR, the
output buffers are enabled and the data from the previous con-
version is available at the outputs during STL = 1. At the end of
the present conversion which is initiated at the rising edge of
WR, STS returns low and the new conversion result is placed on
the output data buffers.
If WR goes low prior to RD the data buffers remain in a high
impedance state and conversion is initiated at the rising edge of
WR. Upon the end of the conversion the STS returns low and
the conversion result is placed on the output data buffers.
Rev. 4.00
130k
1 of 32
26k
COMP
GND Ref.
130k
26k
1/2
VREF
VDAC
12
S
A
R
Figure 7. Equivalent Input Circuit
Quasi Differential Sampling
Method 1
For remote ground sensing where the remote ground does
not change more than 3 V from the A/D ground, connect GND
Ref to the remote ground.
Method 2
Where Method 1 applies to each channel or group of chan-
nels, add a mux to allow connecting the appropriate ground to
GND Ref.
Method 3
Use two parts. Tie both GND Ref pins together and connect
this node to the “common” remote GND. Control the sample
point by connecting each STL through an “OR” gate whose out-
put is “NAND” connect with WR (inverted WR). Use this output
as WR to both WR inputs. By controlling the WR, sample delay
differences between the two converters is minimized. Two parts
from the same date code will further minimize this difference.
Treat one A/D as the (+) terminal and the other as the (–) termi-
nal of the differential signal. Now the difference can be taken
digitally.
11
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| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MP3274.PDF ] | |
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