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PDF AT86RF231 Data sheet ( Hoja de datos )
| Número de pieza | AT86RF231 | |
| Descripción | Low Power 2.4 GHz Radio Transceiver | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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AT86RF230
www.DataSheet4U.com
Features
• High Performance RF-CMOS 2.4 GHz Radio Transceiver Targeted for
IEEE 802.15.4 and ZigBee Applications
• Industry Leading Link Budget (104 dB):
- Programmable Output Power from -17 dBm up to 3 dBm
- Receiver Sensitivity -101 dBm
• Ultra-Low Power Consumption:
- SLEEP: 20 nA
- RX: 15.5 mA
- TX: 16.5 mA (at max Transmit Power of 3 dBm)
• Ultra-Low Supply Voltage (1.8V to 3.6V) with Internal Regulator
• Optimized for Low BoM Cost and Ease of Production:
- Few External Components Necessary (Crystal, Capacitors and Antenna)
• Excellent ESD Robustness
• Easy to Use Interface:
- Registers and Frame Buffer Accessible through Fast SPI
- Only Two Microcontroller GPIO Lines Necessary
- One Interrupt Pin from Radio Transceiver
- Clock Output with Prescaler from Radio Transceiver
• Radio Transceiver Features:
- 128-byte SRAM for Data Buffering
- Programmable Clock Output to Clock the Host Microcontroller or as Timer
Reference
- Integrated TX/RX Switch
- Fully Integrated PLL with on-chip Loop Filter
- Fast PLL Settling Time
- Battery Monitor
- Fast Power-Up Time < 1 ms
• Special IEEE 802.15.4-2003 Hardware Support:
- FCS Computation
- Clear Channel Assessment
- Energy Detection / RSSI Computation
- Automatic CSMA-CA
- Automatic Frame Retransmission
- Automatic Frame Acknowledgement
- Automatic Address Filtering
• Industrial Temperature Range:
- -40°C to 85°C
• I/O and Packages:
- 32-pin Low-Profile QFN
- RoHS/Fully Green
• Compliant to EN 300 328/440, FCC-CFR-47 Part 15, ARIB STD-66, RSS-210
• Compliant to IEEE 802.15.4-2003
Low Power
2.4 GHz
Radio Transceiver
for
ZigBee™ and
IEEE 802.15.4™
Applications
AT86RF230
PRELIMINARY
5131D-ZIGB-12/03/07
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AT86RF230
www.DataSheet4U.com
AVDD, DVDD
AVDD and DVDD are outputs of the internal 1.8V voltage regulators. The voltage
regulators are controlled independently by the radio transceivers state machine and are
activated depending on the current radio transceiver state. The voltage regulators can
be configured for external supply. For details refer to section 9.4.
AVSS, DVSS
AVSS and DVSS are analog and digital ground pins respectively.
The analog and digital power domains should be separated on the PCB, for further
details see application note AVR2005 "Design Considerations for the AT86RF230".
4.2 Analog and RF Pins
RFP, RFN
A differential RF port (RFP/RFN) provides common-mode rejection to suppress the
switching noise of the internal digital signal processing blocks. At the board-level, the
differential RF layout ensures high receiver sensitivity by rejecting any spurious
interspersions originating from other digital ICs such as a microcontroller.
The RF port is designed for a 100Ω differential load. A DC path between the RF pins is
allowed. A DC path to ground or supply voltage is not allowed. Therefore, when
connecting a RF-load providing a DC path to the power supply or to ground, capacitive
coupling is required as indicated in Table 4-2.
A simplified schematic of the RF front end is shown in Figure 4-1.
Figure 4-1. Simplified RF Front-End Schematic
PCB AT86RF230
LNA
RX
RFP
RFN
PA TX
0.9V
CM
Feedback
M0 RXTX
RF port DC values depend on the operating mode. In TRX_OFF state (see section
7.1.2), when the analog front end is disabled, the RF pins are pulled to ground,
preventing a floating voltage.
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AT86RF230
6.1 SPwwI wT.DimataiSnhgeetD4Ue.csocmription
The SPI is designed to work in synchronous or asynchronous mode.
In synchronous mode, the CLKM output of the radio transceiver is used as the master
clock of the microcontroller. In this case the maximum SPI clock frequency is 8 MHz.
In asynchronous mode, the SPI master clock (SCLK) is generated by the
microcontroller itself. The maximum SPI clock rate is limited to 7.5 MHz using this
operating mode. If the clock signal from the radio transceiver pin CLKM is not required,
it may be disabled.
Figure 6-2 and Figure 6-3 illustrate the SPI timing and introduce its parameters. The
corresponding timing parameter definition is given in Table 11-4.
Figure 6-2. SPI Timing, Global Map and Definition of Timing Parameters t5, t6, t8 and t9
Figure 6-3. SPI Timing, Detailed View and Definition of Timing Parameters t0 to t4
SEL
SCLK
MOSI
MISO
t1
t0
t3 t4
Bit 7
Bit 7
t2
Bit 6
Bit 6
Bit 5
Bit 5
The SPI is based on a byte-oriented protocol and is always a bidirectional
communication between master and slave. The SPI master starts the transfer by
asserting SEL = L. Then the master generates eight SPI clock cycles to transfer a byte
to the radio transceiver (via MOSI). At the same time the slave transmits one byte to the
master (via MISO). When the master wants to receive one byte of data from the slave it
must also transmit one byte to the slave. All bytes are transferred MSB first. An SPI
transaction is finished by releasing SEL = H.
A SPI register access consists of two bytes, a Frame Buffer or SRAM access of two or
more bytes, as described in section 6.2.
SEL = L enables the MISO output driver of the radio transceiver. The MSB of MISO is
valid after t1 (see section 11.4 parameter 11.4.3) and is updated at each falling edge of
SCLK. If the MISO output driver is disabled, there is no internal pull-up resistor
connected to the output. Driving the appropriate signal level must be ensured by the
5131D-ZIGB-12/03/07
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| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet AT86RF231.PDF ] | |
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