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PDF ISL6740A Data sheet ( Hoja de datos )

Número de pieza ISL6740A
Descripción Flexible Double-Ended Voltage-Mode PWM Controller
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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No Preview Available ! ISL6740A Hoja de datos, Descripción, Manual

Flexible Double-Ended Voltage-Mode PWM Controller
with Voltage Feed Forward
ISL6740A
The ISL6740A is an enhanced ISL6740 PWM controller
featuring built-in voltage feed forward functionality. It is pin
and feature compatible with the ISL6740 double-ended pulse
width modulating (PWM) voltage-mode controller, allowing
easy drop-in replacement on existing designs.
Voltage feed forward compensates for input voltage variation
without intervention of the feedback control loop. It is
particularly useful in unregulated bus converters and DC
transformers where wide input voltage variation would
otherwise result in large output voltage swings.
In addition to voltage feed forward compensation, the
ISL6740A features an extremely flexible oscillator that allows
precise control of frequency, duty cycle, and deadtime.
Deadtimes of under 40ns are easily achievable.
This advanced BiCMOS design features low operating current,
adjustable switching frequency up to 1MHz, adjustable
soft-start, internal and external over-temperature protection,
fault annunciation, and a bidirectional SYNC signal that allows
the oscillator to be locked to paralleled units or to an external
clock for noise sensitive applications.
Ordering Information
PART
NUMBER
(Notes 1, 2, 3)
PART
TEMP.
MARKING RANGE (°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6740AIVZA 6740 AIVZ -40 to +105 16 Ld TSSOP M16.173
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details
on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-
free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-
free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information
page for ISL6740A. For more information on MSL please see
techbrief TB363.
Features
• Input Voltage Feed Forward Compensation
• Precision Duty Cycle and Deadtime Control
• Adjustable Delayed Overcurrent Shutdown and Re-Start
• Adjustable Short Circuit Shutdown and Re-Start
• Adjustable Oscillator Frequency Up to 2MHz
• Bidirectional Synchronization
• Adjustable Input Undervoltage Lockout/Inhibit
• Tight Tolerance Voltage Reference Over Line, Load, and
Temperature
• Adjustable Soft-Start
• Fault Signal
• 95µA Startup Current
• Internal Over-Temperature Protection
• System Over-Temperature Protection Using a Thermistor or
Sensor
• Pb-free and ELV, WEEE, RoHS Compliant
Applications
• Telecom and Datacom Power
• Wireless Base Station Power
• File Server Power
• Industrial Power Systems
• DC Transformers and Bus Converters
Pin Configuration
ISL6740A
(16 LD TSSOP)
TOP VIEW
OUTA 1
GND 2
SCSET 3
CT 4
SYNC 5
CS 6
VERROR 7
UV/FF 8
16 OUTB
15 VREF
14 VDD
13 RTD
12 RTC
11 OTS
10 FAULT
9 SS
February 9, 2012
FN9195.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2005, 2011, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

1 page




ISL6740A pdf
ISL6740A
Absolute Maximum Ratings
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +20.0V
OUTA, OUTB, Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VREF
VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 6.0V
Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5A
ESD Classification
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . . . . . 1500V
Charged Device Model (Per EOS/ESD DS5.3, 4/14/93). . . . . . . . 1000V
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
16 Ld TSSOP (Notes 4, 5) . . . . . . . . . . . . . .
98
30
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . -55°C to 150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . . . -65°C to 150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range
ISL6740AIVx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 105°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . . . . 9VDC - 16 VDC
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For θJC, the “case temp” location is taken at the package top center.
6. All voltages are with respect to GND.
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on
page 2 and Typical Application Schematics on page 3 and page 4. 9V < VDD < 20 V, RTD = 51.1kΩ, RTC = 10kΩ, CT = 470pF, TA = -40°C to 105°C,
Typical values are at TA = 25°C. Boldface limits apply over the operating temperature range, -40°C to +105°C.
PARAMETER
TEST CONDITIONS
MIN MAX
(Note 7) TYP (Note 7) UNITS
SUPPLY VOLTAGE
Start-Up Current, IDD
Operating Current, IDD
UVLO START Threshold
VDD < START Threshold
RLOAD, COUTA,B = 0
COUTA,B = 1nF
-
-
-
6.50
95
5.0
7.0
7.25
140
8.0
12.0
8.00
µA
mA
mA
V
UVLO STOP Threshold
6.00
6.75
7.50
V
Hysteresis
0.35
0.50
0.75
V
REFERENCE VOLTAGE
Overall Accuracy
Long Term Stability
Fault Voltage
IVREF = 0, -20mA
TA = 125°C, 1000 hours
4.900
-
4.10
5.000
3
4.55
5.050
-
4.75
V
mV
V
VREF Good Voltage
4.25
4.75
VREF
-0.05
V
Hysteresis
75 165 250 mV
Operational Current (Source)
-20 -
- mA
Operational Current (Sink)
5 - - mA
Current Limit
-25
-
-100
mA
CURRENT SENSE
Current Limit Threshold
CS to OUT Delay
VERROR = VREF
0.55 0.6 0.65
- 35 50
V
ns
CS Sink Current
- 10 - mA
Input Bias Current
-1.00
-
1.00
µA
SCSET Input Impedance
1 - - MΩ
5 FN9195.3
February 9, 2012

5 Page





ISL6740A arduino
ISL6740A
VIN
R1
R3
R2
1.00V +
-
10μA
ON
FIGURE 5. UV HYSTERESIS
As VIN decreases to a UV condition, the threshold level is:
VIN(DOWN) = R-----1---R--+--2---R----2--
V
(EQ. 7)
The hysteresis voltage, ΔV, is:
ΔV
=
105
R
1
+
R3
R-----1---R--+--2---R----2--⎠⎞
V
(EQ. 8)
Setting R3 equal to zero results in the minimum hysteresis,
and yields:
ΔV = 105 R1
V
(EQ. 9)
As VIN increases from a UV condition, the threshold level is:
VIN(UP) = VIN(DOWN) + ΔV
V
(EQ. 10)
Output voltage variation caused by changes in the supply
voltage may be virtually removed through a technique known
as feed forward compensation. Using feed forward, the duty
cycle is directly modulated based on changes in the input
voltage only. No closed loop feedback system is required. The
feed forward circuit uses the voltage applied to the UV/FF pin
to modulate the oscillator ramp amplitude with minimal effect
on the switching frequency and deadtime of the oscillator. The
voltage feed forward operates over a 3:1 input voltage range.
VUV/FF
VERROR
CT
OUTA
OUTB
FIGURE 6. FEED FORWARD BEHAVIOR
The voltage applied to the UV/FF pin is multiplied by 0.8 and
output on the RTC and RTD pins. This voltage is also summed
with the CT valley threshold voltage (0.8 V) to create the CT
peak threshold voltage. As the voltage applied to UV/FF varies,
the CT peak voltage and the CT charge and discharge currents
vary, all in direct proportion to each other. The result is an
amplitude modulated sawtooth waveform on CT that is
frequency invariant.
The voltage amplitude of CT ranges from 1.6V to 4.2V as the
voltage on UV increases. The UV threshold defines the
minimum amplitude of CT and corresponds to maximum duty
cycle operation.
For unregulated bus converters and DC transformers, feed
forward can compensate for input voltage variations without a
closed loop feedback network. A resistive voltage divider from
VREF to VERROR sets the feed forward control voltage. For
example, if the desired duty cycle at the minimum operating
voltage is 90%, then:
VERROR = Dmax(VUV FF 0.8) + 0.8
V
(EQ. 11)
= 0.9(1.0 0.8) + 0.8 = 1.52
V
Overcurrent Protection
There are two overcurrent protection mechanisms in the
ISL6740A, one for light overcurrent and one for heavy over
load. They are referred to, respectively, as overcurrent
protection and short circuit protection.
OVERCURRENT OPERATION
Overcurrent delayed shutdown is enabled once the soft-start
cycle is complete. If an overcurrent condition is detected, the
soft-start charging current source is disabled and the soft-start
capacitor is allowed to discharge through a 15µA source. At
the same time a 50µs re-triggerable one-shot timer is
activated. It remains active for 50µs after the overcurrent
condition ceases. If the soft-start capacitor discharges by more
then 0.25V to 4.25V, the output is disabled and the Fault signal
asserted. This state continues until the soft-start voltage
reaches 270mV, at which time a new soft-start cycle is
initiated. If the overcurrent condition stops at least 50µs prior
to the soft-start voltage decreasing to 4.25V, the soft-start
charging currents revert to normal operation and the soft-start
voltage is allowed to recover.
4.5 V
SS
0.6 V OC
CS
OUTA
OUTB
FIGURE 7. PULSE-BY-PULSE OC BEHAVIOR DURING SS
Figure 7 shows the overcurrent behavior during SS. Although
an overcurrent condition exists, a shutdown is not allowed prior
to completion of the SS cycle. Only peak current limit operates
during the soft-start cycle. If the overcurrent condition were to
continue beyond the soft-start cycle, a delayed overcurrent
shutdown would occur as shown in Figure 8.
11 FN9195.3
February 9, 2012

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