|
|
PDF ISL6742 Data sheet ( Hoja de datos )
| Número de pieza | ISL6742 | |
| Descripción | Advanced Double-Ended PWM Controller | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ISL6742 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
|
No Preview Available !
®
Data Sheet
July 25, 2005
ISL6742
www.DataSheet4U.com
FN9183.1
Advanced Double-Ended PWM Controller
The ISL6742 is a high-performance double-ended PWM
controller with advanced synchronous rectifier control and
current limit features. It is suitable for both current- and
voltage-mode control methods.
The ISL6742 includes complemented PWM outputs for
synchronous rectifier (SR) control. The complemented
outputs may be dynamically advanced or delayed relative to
the main outputs using an external control voltage.
Its advanced current sensing circuitry employs sample and
hold methods to provide a precise average current signal.
Suitable for average current limiting, a technique which
virtually eliminates the current tail-out common to peak
current limiting methods, it is also applicable to current
sharing circuits and average current mode control.
This advanced BiCMOS design features an adjustable
oscillator frequency up to 2MHz, internal over-temperature
protection, precision deadtime control, and short
propagation delays. Additionally, Multi-Pulse Suppression
ensures alternating output pulses at low duty cycles where
pulse skipping may occur.
Ordering Information
TEMP. RANGE
PKG. DWG.
PART NUMBER
(°C)
PACKAGE
#
ISL6742AAZA
(See Note)
-40 to 105
16 Ld QSOP M16.15A
(Pb-free)
Add -T suffix to part number for tape and reel packaging
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinout
ISL6742 (QSOP)
TOP VIEW
VREF 1
VERR 2
RTD 3
CT 4
FB 5
RAMP 6
CS 7
IOUT 8
16 SS
15 VADJ
14 VDD
13 OUTA
12 OUTB
11 OUTAN
10 OUTBN
9 GND
Features
• Synchronous Rectifier Control Outputs with Adjustable
Delay/Advance
• Adjustable Average Current Signal
• 3% Tolerance Cycle-by-Cycle Peak Current Limit
• Fast Current Sense to Output Delay
• Adjustable Oscillator Frequency Up to 2MHz
• Adjustable Deadtime Control
• Voltage- or Current-Mode Operation
• Separate RAMP and CS Inputs for Voltage Feed Forward
or Current-Mode Applications
• Tight Tolerance Error Amplifier Reference Over Line,
Load, and Temperature
• 175µA Start-up Current
• Supply UVLO
• Adjustable Soft-Start
• 70ns Leading Edge Blanking
• Multi-Pulse Suppression
• Internal Over Temperature Protection
• Pb-free and ELV, WEEE, RoHS Compliant
Applications
• Half-Bridge, Full-Bridge, Interleaved Forward, and Push-
Pull Converters
• Telecom and Datacom Power
• Wireless Base Station Power
• File Server Power
• Industrial Power Systems
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6742
Absolute Maximum Ratings
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . GND - 0.3V to +20.0V
OUTxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VDD
Signal Pins . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VREF + 0.3V
VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6.0V
Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1A
ESD Classification
Human Body Model (Per MIL-STD-883 Method 3015.7) . . .2000V
Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . .1000V
Thermal Information
www.DataSheet4U.com
Thermal Resistance Junction to Ambient (Typical)
θJA (°C/W)
16 Lead QSOP (Note 1). . . . . . . . . . . . . . . . . . . . . .
95
Maximum Junction Temperature . . . . . . . . . . . . . . . . -55°C to 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(QSOP- Lead Tips Only)
Operating Conditions
Temperature Range
ISL6742AAxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 105°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . 9-16 VDC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. All voltages are with respect to GND.
Electrical Specifications
PARAMETER
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
schematic. 9V < VDD < 20V, RTD = 10.0kΩ, CT = 470pF, TA = -40°C to 105°C (Note 3), Typical values are at
TA = 25°C
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY VOLTAGE
Supply Voltage
- - 20 V
Start-Up Current, IDD
Operating Current, IDD
UVLO START Threshold
VDD = 5.0V
RLOAD, COUT = 0
-
-
8.00
175
7.5
8.75
400
12.0
9.00
µA
mA
V
UVLO STOP Threshold
6.50 7.00 7.50
V
Hysteresis
- 1.75 -
V
REFERENCE VOLTAGE
Overall Accuracy
Long Term Stability
Operational Current (source)
IVREF = 0 - 10mA
TA = 125°C, 1000 hours (Note 4)
4.850
-
-10
5.000
3
-
5.150
-
-
V
mV
mA
Operational Current (sink)
5 - - mA
Current Limit
VREF = 4.85V
-15
-
-100
mA
CURRENT SENSE
Current Limit Threshold
VERR = VREF
0.97 1.00 1.03
V
CS to OUT Delay
Excl. LEB (Note 4)
- 35 50 ns
Leading Edge Blanking (LEB) Duration
(Note 4)
50 70 100 ns
CS to OUT Delay + LEB
CS Sink Current Device Impedance
Input Bias Current
IOUT Sample and Hold Buffer Amplifier Gain
IOUT Sample and Hold VOH
IOUT Sample and Hold VOL
TA = 25°C
VCS = 1.1V
VCS = 0.3V
TA = 25°C
VCS = 1.00V, ILOAD = -300µA
VCS = 0.00V, ILOAD = 10µA
- - 130 ns
- - 20 Ω
-1.0 - 1.0 µA
4.00 4.09 4.15 V/V
3.9 - - V
- - 0.3 V
5 FN9183.1
July 25, 2005
5 Page 
ISL6742
The average current signal on IOUT remains accurate
provided that the output inductor current is continuous (CCM
operation). Once the inductor current becomes
discontinuous (DCM operation), IOUT represents 1/2 the
peak inductor current rather than the average current. This
occurs because the sample and hold circuitry is active only
during the on time of the switching cycle. It is unable to
detect when the inductor current reaches zero during the off
time.
If average overcurrent limit is desired, IOUT may be used
with the available error amplifier of the ISL6742. Typically
IOUT is divided down and filtered as required to achieve the
desired amplitude. The resulting signal is input to the current
error amplifier (IEA). The IEA is similar to the voltage EA
found in most PWM controllers, except it cannot source
current. Instead, VERR has a separate internal 1mA pull-up
current source.
Configure the IEA as an integrating (Type I) amplifier using
the internal 0.6V reference. The voltage applied at FB is
integrated against the 0.6V reference. The resulting signal,
VERR, is applied to the PWM comparator where it is
compared to the sawtooth voltage on RAMP. If FB is less
than 0.6V, the IEA will be open loop (can’t source current),
VERR will be at a level determined by the voltage loop, and
the duty cycle is unaffected. As the output load increases,
IOUT will increase, and the voltage applied to FB will
increase until it reaches 0.6V. At this point the IEA will
reduce VERR as required to maintain the output current at
the level that corresponds to the 0.6V reference. When the
output current again drops below the average current limit
threshold, the IEA returns to an open loop condition, and the
duty cycle is again controlled by the voltage loop.
The average current control loop behaves much the same
as the voltage control loop found in typical power supplies
except it regulates current rather than voltage.
The EA available on the ISL6742 may also be used as the
voltage EA for the voltage feedback control loop rather than
the current EA as described above. An external op-amp may
be used as either the current or voltage EA providing the
circuit is not allowed to source current into VERR. The
external EA must only sink current, which may be
accomplished by adding a diode in series with its output.
The 4x gain of the sample and hold buffer allows a range of
150 - 1000mV peak on the CS signal, depending on the
resistor divider placed on IOUT. The overall bandwidth of the
average current loop is determinedwbwy wth.eDianttaeSghraeteint4gUc.cuorrment
EA compensation and the divider on IOUT.
C10
150 - 1000 mV
R6
1 ISL6742
2 VERR
3
4
5 FB
-
6 0.6V +
7 CS
S&H
4x
8 IOUT
R5
16
15
14
13
12
11
10
9
R4
FIGURE 7. AVERAGE OVERCURRENT IMPLEMENTATION
The current EA cross-over frequency, assuming R6 >>
(R4||R5), is
fCO = 2----π-----⋅---R-----16-----⋅---C-----1---0--
Hz
(EQ. 7)
where fCO is the cross-over frequency. A capacitor in parallel
with R4 may be used to provide a double-pole roll-off.
The average current loop bandwidth is normally set to be
much less than the switching frequency, typically less than
5kHz and often as slow as a few hundred hertz or less. This
is especially useful if the application experiences large
surges. The average current loop can be set to the steady
state overcurrent threshold and have a time response that is
longer than the required transient. The peak current limit can
be set higher than the expected transient so that it does not
interfere with the transient, but still protects for short-term
larger faults. In essence a 2-stage overcurrent response is
possible.
The peak overcurrent behavior is similar to most other PWM
controllers. If the peak current exceeds 1.0V, the active
output pulse is terminated immediately.
If voltage-mode control is used in a bridge topology, it should
be noted that peak current limit results in inherently unstable
operation. DC blocking capacitors used in voltage-mode
bridge topologies become unbalanced, as does the flux in
the transformer core. The average overcurrent circuitry
prevents this behavior by maintaining symmetric duty cycles
for each half-cycle. If the average current limit circuitry is not
used, a latching overcurrent shutdown method using
external components is recommended.
The CS to output propagation delay is increased by the
leading edge blanking (LEB) interval. The effective delay is
the sum of the two delays and is 130ns maximum.
11 FN9183.1
July 25, 2005
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ISL6742.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ISL6740 | Flexible Double Ended Voltage and Current Mode PWM Controllers | Intersil Corporation |
| ISL6740A | Flexible Double-Ended Voltage-Mode PWM Controller | Intersil Corporation |
| ISL6741 | Flexible Double Ended Voltage and Current Mode PWM Controllers |  Intersil |
| ISL6742 | Advanced Double-Ended PWM Controller | Intersil Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |