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PDF MT48H8M32LF Data sheet ( Hoja de datos )

Número de pieza MT48H8M32LF
Descripción Mobile Low-Power SDR SDRAM
Fabricantes Micron Technology　
Logotipo Micron Technology Logotipo



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No Preview Available ! MT48H8M32LF Hoja de datos, Descripción, Manual

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Features
Mobile Low-Power SDR SDRAM
MT48H16M16LF – 4 Meg x 16 x 4 banks
MT48H8M32LF – 2 Meg x 32 x 4 banks
Features
• VDD/VDDQ = 1.7–1.95V
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal, pipelined operation; column address can
be changed every clock cycle
• Four internal banks for concurrent operation
• Programmable burst lengths: 1, 2, 4, 8, and continu-
ous
• Auto precharge, includes concurrent auto precharge
• Auto refresh and self refresh modes
• LVTTL-compatible inputs and outputs
• On-chip temperature sensor to control self refresh
rate
• Partial-array self refresh (PASR)
• Deep power-down (DPD)
• Selectable output drive strength (DS)
• 64ms refresh period
Options
• VDD/VDDQ: 1.8V/1.8V
• Addressing
– Standard addressing option
• Configuration
– 16 Meg x 16 (4 Meg x 16 x 4 banks)
– 8 Meg x 32 (2 Meg x 32 x 4 banks)
• Plastic “green” packages
– 54-ball VFBGA (8mm x 9mm)1
– 90-ball VFBGA (8mm x 13mm)2
• Timing – cycle time
– 6ns @ CL = 3
– 7.5ns @ CL = 3
• Operating temperature range
– Commercial (0˚C to +70˚C)
– Industrial (–40˚C to +85˚C)
• Revision
Marking
H
LF
16M16
8M32
BF
B5
-6
-75
None
IT
:H
Notes: 1. Available only for x16 configuration.
2. Available only for x32 configuration.
Table 1: Configuration Addressing
Architecture
Number of banks
Bank address balls
Row address balls
Column address balls
16 Meg x 16
4
BA0, BA1
A[12:0]
A[8:0]
8 Meg x 32
4
BA0, BA1
A[11:0]
A[8:0]
Table 2: Key Timing Parameters
Speed
Grade
-6
-75
Clock Rate (MHz)
CL = 2 CL = 3
104 166
104 133
Access Time
CL = 2 CL = 3
8.0ns
5.0ns
8.0ns
5.4ns
Note: 1. CL = CAS (READ) latency
PDF: 09005aef834c13d2
256mb_mobile_sdram_y36n.pdf - Rev. J 09/10 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.

1 page




MT48H8M32LF pdf
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Features
List of Figures
Figure 1: 256Mb Mobile LPSDR Part Numbering ............................................................................................... 2
Figure 2: Functional Block Diagram ................................................................................................................. 9
Figure 3: 54-Ball VFBGA (Top View) ............................................................................................................... 10
Figure 4: 90-Ball VFBGA (Top View) ............................................................................................................... 11
Figure 5: 54-Ball VFBGA (8mm x 9mm) .......................................................................................................... 13
Figure 6: 90-Ball VFBGA (8mm x 13mm) ......................................................................................................... 14
Figure 7: Typical Self Refresh Current vs. Temperature .................................................................................... 19
Figure 8: ACTIVE Command .......................................................................................................................... 28
Figure 9: READ Command ............................................................................................................................. 29
Figure 10: WRITE Command ......................................................................................................................... 30
Figure 11: PRECHARGE Command ................................................................................................................ 31
Figure 12: Initialize and Load Mode Register .................................................................................................. 39
Figure 13: Mode Register Definition ............................................................................................................... 40
Figure 14: CAS Latency .................................................................................................................................. 43
Figure 15: Extended Mode Register Definition ................................................................................................ 44
Figure 16: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3 .......................................................... 46
Figure 17: Consecutive READ Bursts .............................................................................................................. 48
Figure 18: Random READ Accesses ................................................................................................................ 49
Figure 19: READ-to-WRITE ............................................................................................................................ 50
Figure 20: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 51
Figure 21: READ-to-PRECHARGE .................................................................................................................. 51
Figure 22: Terminating a READ Burst ............................................................................................................. 52
Figure 23: Alternating Bank Read Accesses ..................................................................................................... 53
Figure 24: READ Continuous Page Burst ......................................................................................................... 54
Figure 25: READ – DQM Operation ................................................................................................................ 55
Figure 26: WRITE Burst ................................................................................................................................. 56
Figure 27: WRITE-to-WRITE .......................................................................................................................... 57
Figure 28: Random WRITE Cycles .................................................................................................................. 58
Figure 29: WRITE-to-READ ............................................................................................................................ 58
Figure 30: WRITE-to-PRECHARGE ................................................................................................................. 59
Figure 31: Terminating a WRITE Burst ............................................................................................................ 60
Figure 32: Alternating Bank Write Accesses ..................................................................................................... 61
Figure 33: WRITE – Continuous Page Burst ..................................................................................................... 62
Figure 34: WRITE – DQM Operation ............................................................................................................... 63
Figure 35: READ With Auto Precharge Interrupted by a READ ......................................................................... 65
Figure 36: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 66
Figure 37: READ With Auto Precharge ............................................................................................................ 67
Figure 38: READ Without Auto Precharge ....................................................................................................... 68
Figure 39: Single READ With Auto Precharge .................................................................................................. 69
Figure 40: Single READ Without Auto Precharge ............................................................................................. 70
Figure 41: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 71
Figure 42: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 71
Figure 43: WRITE With Auto Precharge ........................................................................................................... 72
Figure 44: WRITE Without Auto Precharge ..................................................................................................... 73
Figure 45: Single WRITE With Auto Precharge ................................................................................................. 74
Figure 46: Single WRITE Without Auto Precharge ............................................................................................ 75
Figure 47: Auto Refresh Mode ........................................................................................................................ 77
Figure 48: Self Refresh Mode .......................................................................................................................... 79
Figure 49: Power-Down Mode ........................................................................................................................ 80
Figure 50: Clock Suspend During WRITE Burst ............................................................................................... 82
PDF: 09005aef834c13d2
256mb_mobile_sdram_y36n.pdf - Rev. J 09/10 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.

5 Page





MT48H8M32LF arduino
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Ball Assignments and Descriptions
Figure 4: 90-Ball VFBGA (Top View)
1 234 56789
A
DQ26 DQ24 VSS
B
DQ28 VDDQ VSSQ
C
VSSQ DQ27 DQ25
D
VSSQ DQ29 DQ30
E
VDDQ DQ31 NC
F
VSS DQM3 A3
G
A4 A5 A6
H
A7 A8 A12
J
CLK CKE
A9
K
DQM1 DNU1 NC
L
VDDQ DQ8
VSS
M
VSSQ DQ10 DQ9
N
VSSQ DQ12 DQ14
P
DQ11 VDDQ VSSQ
R
DQ13 DQ15 VSS
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC DQ16 VSSQ
A2 DQM2 VDD
A10 A0
A1
A13 BA1 A11
BA0 CS# RAS#
CAS# WE# DQM0
VDD
DQ7
VSSQ
DQ6 DQ5 VDDQ
DQ1 DQ3 VDDQ
VDDQ VSSQ
DQ4
VDD DQ0 DQ2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Note: 1. The K2 pin must be connected to VSS, VSSQ, or left floating.
PDF: 09005aef834c13d2
256mb_mobile_sdram_y36n.pdf - Rev. J 09/10 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.

11 Page







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