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PDF LS037V7DW01 Data sheet ( Hoja de datos )

Número de pieza LS037V7DW01
Descripción TFT LCD Module
Fabricantes Sharp Microelectronics 
Logotipo Sharp Microelectronics Logotipo



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PRODUCT SPECIFICATIONS
AVC Liquid Crystal Displays Group
LS037V7DW01
TFT-LCD Module
Spec. Issue Date: May 17, 2006
No: LCP-06008A

1 page




LS037V7DW01 pdf
(1) Application
This literature applies to LS037V7DW01.
LCP-06008A-2
(2) Overview
This module is a color transflective and active matrix LCD module incorporating CG-Silicon TFT
(Continuous Grain-Silicon Thin Film Transistor). It is composed of a color TFT-LCD panel, driver ICs
(with control Function), an FPC(with DC-DC Converter), a back light, a touch panel and a back sealed casing.
It is composed control circuit. Graphics and texts can be displayed on a 480×3×640 dots panel with
262,144 colors by supplying.
This LCD module has multi resolution and multi colors functions. A resolution mode is selective in
VGA (480H×640V) or QVGA (240H×320V). A Color mode is selective in 262,144 colors (18bit RGB) or
8 colors (3bit RGB).
It is a wide viewing-angle-mode (Vertical viewing angle:(±80°) Horizontal viewing angle: (±80°) ,CR5).
(3) Mechanical specifications
Table 1
Parameter
Specifications
Units
Remarks
Screen size (Diagonal)
9.4 [3.7”] Diagonal
cm
Display active area
56.16H×74.88V
mm
Touch panel active area
57.4H×76.1V
mm
Pixel format
480(H)×640(V)
(1 pixel = R+G+B dots)
pixels
Dot pitch
0.039H×0.117V
mm
Pixel configuration
R,G,B vertical stripe
Display mode
Normally Black
Unit outline dimension
65.0(W)×89.2(H)×4.4(D)
mm Note3-1
Mass
Typ.48
Surface hardness
3H
Note 3-1Excluding protrusion. For detailed measurements and tolerances, please refer to Fig. 1.
(4) Pixel configuration
(1,1)
RGB
(m,1)
LCD/LED/TP
FPC
1
51
(1,n)
Display area
(m,n)
VGA mode m=480,n=640
QVGA modem=240,n=320

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LS037V7DW01 arduino
Note 7-4HCYC = HSYNC Period(VGA:Typ.648CLK, QVGA:Typ.324CLK)
Note 7-5VSYNC,HSYNC,CLK,R0R5,G0G5,B0B5,DEN terminals are applied.
LCP-06008A-8
tRISE1
Input Signal 0.1VDD
0.9VDD
tFALL1
0.9VDD
0.1VDD
Fig 7-1 Input Signal Rising/Falling Timing
Note 7-6INI,RESB terminals are applied.
tRISE2
Input Signal 0.1VDD
0.9VDD
tFALL2
0.9VDD
0.1VDD
Fig 7-2 Input Signal Rising/Falling Timing
Note 7-7Reset Signal Timing chart
RESB
tRESW
Fig 7-3 Reset Timing Signal
7-3)Power consumption
Measurement condition : Vsync=59.94Hz,Hsync=38.84kHz,CLK=25.17MHz,Ta=25(VGA Mode)
Table 7
(when conventional scan mode)
Parameter
Sym Conditions MIN TYP MAX Unit Remarks
VSHD Total(Digital+Analog) ISHD VSHD=+3.3V 45 75 mA Note7-8
Note 7-8White Pattern

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