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PDF MPC92432 Data sheet ( Hoja de datos )
| Número de pieza | MPC92432 | |
| Descripción | 1360 MHz Dual Output LVPECL Clock Synthesizer | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order number: MPC92432
Rev 0, 06/2004
Product Preview
1360 MHz Dual Output LVPECL
Clock Synthesizer
The MPC92432 is a 3.3V compatible, PLL based clock synthesizer targeted
for high performance clock generation in mid-range to high-performance
telecom, networking, and computing applications. With output frequencies
from 21.25 MHz to 1360 MHz and the support of two differential PECL output
signals, the device meets the needs of the most demanding clock applications.
MPC92432
1360 MHz LOW VOLTAGE
CLOCK SYNTHESIZER
Features
• 21.25 MHz to 1360 MHz synthesized clock output signal
• Two differential, LVPECL-compatible high-frequency outputs
• Output frequency programmable through 2-wire I2C bus or parallel
interface
• On-chip crystal oscillator for reference frequency generation
• Alternative LVCMOS compatible reference clock input
• Synchronous clock stop functionality for both outputs
• LOCK indicator output (LVCMOS)
• LVCMOS compatible control inputs
• Fully integrated PLL
• 3.3-V power supply
• 48-lead LQFP
• SiGe Technology
• Ambient temperature range: –40°C to +85°C
SCALE 2:1
FA SUFFIX
48-LEAD LQFP PACKAGE
CASE 932
Applications
• Programmable clock source for server, computing, and telecommunication systems
• Frequency margining
• Oscillator replacement
Functional Description
The MPC92432 is a programmable high-frequency clock source (clock synthesizer). The internal PLL generates a high-frequency
output signal based on a low-frequency reference signal. The frequency of the output signal is programmable and can be changed
on the fly for frequency margining purpose.
The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. Alternatively, a LVCMOS com-
patible clock signal can be used as a PLL reference signal. The frequency of the internal crystal oscillator is divided by a selectable
divider and then multiplied by the PLL. The VCO within the PLL operates over a range of 1360 to 2720 MHz. Its output is scaled by
a divider that is configured by either the I2C or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL pre-divider P, the
feedback-divider M, and the PLL post-divider N determine the output frequency. The feedback path of the PLL is internal.
The PLL post-divider N is configured through either the I2C or the parallel interfaces, and can provide one of six division ratios (2,
4, 8, 16, 32, 64). This divider extends the performance of the part while providing a 50% duty cycle. The high-frequency outputs, QA
and QB, are differential and are capable of driving a pair of transmission lines terminated 50 Ω to VCC – 2.0 V. The second high-fre-
quency output, QB, can be configured to run at either 1x or 1/2x of the clock frequency or the first output (QA). The positive supply
voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise induced jitter.
The configuration logic has two sections: I2C and parallel. The parallel interface uses the values at the M[9:0], NA[2:0], NB, and P
parallel inputs to configure the internal PLL dividers. The parallel programming interface has priority over the serial I2C interface. The
serial interface is I2C compatible and provides read and write access to the internal PLL configuration registers. The lock state of the
PLL is indicated by the LVCMOS-compatible LOCK outputs.
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Motorola, Inc. 2004
For More Information On This Product,
Go to: www.freescale.com
1 page  
Freescale Semiconductor, Inc.
MPC92432
Table 3. General Specifications
Symbol
Characteristics
VTT Output Termination Voltage
MM ESD Protection (Machine model)
HBM ESD Protection (Human body model)
LU Latch-Up Immunity
CIN Input Capacitance
θJA Thermal Resistance Junction to Ambient
JESD 51-3, single layer test board
Min
—
200
2000
200
—
—
JESD 51-6, 2S2P multilayer test board
θJC LQFP 32 Thermal Resistance Junction to Case
—
Typ
VCC – 2
—
—
—
4.0
—
—
Max
—
—
—
—
—
TBD
TBD
Unit Condition
V
V
V
mA
pF Inputs
°C/W
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
°C/W MIL-SPEC 883E
Method 1012.1
Table 4. Absolute Maximum Ratings1
Symbol
Characteristics
Min
Max Unit
Condition
VCC Supply Voltage
–0.3 3.9 V
VIN DC Input Voltage
–0.3
VCC+0.3
V
VOUT DC Output Voltage
–0.3
VCC+0.3
V
IIN DC Input Current
— ±20 mA
IOUT DC Output Current
— ±50 mA
TS Storage temperature
–65 125 °C
1. Absolute maximum continuos ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not
implied.
TIMING SOLUTIONS
5
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MOTOROLA
5 Page 
Freescale Semiconductor, Inc.
MPC92432
recommended to write the INC, DEC commands only after a
valid PLL configuration is achieved. INC and DEC only affect
the M-divider of the PLL (PLL feedback). Applying INC and
DEC commands can result in a PLL configuration beyond the
specified lock range and the PLL may loose lock. The
MPC92432 does not verify the validity of any commands such
as LOAD, INC, and DEC. The INC and DEC commands change
the PLL feedback divider without updating PLL_L and PLL_H.
Table 16. CMD (0xF0): PLL Command (Write-Only)
Command
INC
DEC
LOAD
GET
Op-Code
xxxx0001b
(0x01)
xxxx0010b
(0x02)
xxxx0100b
(0x04)
xxxx1000b
(0x08)
Description
Increase internal PLL frequency
M:=M+1
Decrease internal PLL frequency
M:=M-1
Update the PLL divider config.
PLL divider M, N, P:=PLL_L, PLL_H
Update the configuration registers
PLL_L, PLL_H:=PLL divider M, N, P
I2C — Register Access in Parallel Mode
The MPC92432 supports the configuration of the synthesizer
through the parallel interlace (PLOAD = 0) and serial interface
(PLOAD = 1). Register contents and the divider configurations
are not changed when the user switches from parallel mode to
serial mode. However, when switching from serial mode to
parallel mode, the PLL dividers immediately reflect the logical
state of the hardware pins M[9:0], NA[2:0], NB, and P.
Applications using the parallel interface to obtain a PLL
configuration can use the serial interface to verify the divider
settings. In parallel mode (PLOAD = 0), the MPC92432 allows
read-access to PLL_L and PLL_H through I2C (if PLOAD = 0,
the current PLL configuration is stored in PLL_L, PLL_H. The
GET command is not necessary and also not supported in
parallel mode). After changing from parallel to serial mode
(PLOAD = 1), the last PLL configuration is still stored in PLL_L,
PLL_H. The user now has full write and read access to both
configuration registers through the I2C bus and can change the
configuration at any time.
Table 17. PLL Configuration in Parallel and Serial Modes
PLL
Configuration
M[9:0]
NA[2:0]
NB
P
LOCK status
Parallel
Set pins M9–M0
Set pins NA2...NA0
Set pin NB
Set bit P in PLL_H
LOCK pin 26
Serial (Registers
PLL_L, PLL_H)
M[9:0] (R/W)
NA[2:0] (R/W)
NB (R/W)
P (R/W)
LOCK (Read only)
Programming the I2C Interface
Table 18. I2C Slave Address
Bit 7 6 5 4
Value 1 0 1 1
32 1 0
0 Pin Pin R/W
ADR1 ADR0
The 7-bit I2C slave address of the MPC92432 synthesizer is
a combination of a 5-bit fixed addresses and two variable bits
which are set by the hardware pins ADR[1:0]. Bit 0 of the
MPC92432 slave address is used by the bus controller to select
either the read or write mode.’0’ indicates a transmission
(I2C-WRITE) to the MPC92432.’1’ indicates a request for data
(I2C-READ) from the synthesizer. The hardware pins ADR1 and
ADR0 and should be individually set by the user to avoid
address conflicts of multiple MPC92432 devices on the same
I2C bus.
Write Mode (R/W = 0)
The configuration registers are written by the bus controller
by the initiation of a write transfer with the MPC92432 slave
address (first byte), followed by the address of the configuration
register (second byte: 0x00, 0x01 or 0xF0), and the
configuration data byte (third byte). This transfer may be
followed by writing more registers by sending the configuration
register address followed by one data byte. Each byte sent by
the bus controller is acknowledged by the MPC92432. The
transfer ends by a stop bit sent by the bus controller. The
number of configuration data bytes and the write sequence are
not restricted.
Table 19. Complete Configuration Register Write Transfer
1 bit
Start
Master
7 bits
Slave address
10110xx1
Master
1 bit 1 bit
R/W ACK
0
Mast Slave
1. xx = state of ADR1, ADR0 pins
8 bits
&PLL_H
0x01
Master
1 bit
ACK
8 bits
Config-Byte 1
Data
1 bit
ACK
Slave
Master
Slave
8 bits
&PLL_L
0x00
Master
1 bit
ACK
8 bits
Config-Byte 2
Data
1 bit
ACK
1 bit
Stop
Slave
Master
Slave Mast
TIMING SOLUTIONS
11
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MOTOROLA
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| PDF Descargar | [ Datasheet MPC92432.PDF ] | |
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