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PDF AND8282D Data sheet ( Hoja de datos )
| Número de pieza | AND8282D | |
| Descripción | Implementing Cost Effective and Robust Power Factor Correction | |
| Fabricantes | ON Semiconductor | |
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AND8282/D
Implementing Cost
Effective and Robust Power
Factor Correction with the
NCP1606
Prepared by: Jon Kraft
ON Semiconductor
http://onsemi.com
APPLICATION NOTE
Introduction
The NCP1606 is a voltage mode power factor correction
(PFC) controller designed to drive cost−effective
pre−converters to meet input line harmonic regulations. The
device operates in Critical Conduction Mode (CRM) for
optimal performance in applications up to about 300 W. Its
voltage mode scheme enables it to obtain unity power factor
without the need for a line sensing network. The output
voltage is accurately controlled with a built in high precision
error amplifier. The controller also implements a
comprehensive array of safety features for robust designs.
This application note describes the design and
implementation of a 400 V, 100 W, CRM Boost PFC
pre−converter using the NCP1606. The converter exhibits
high power factor, low standby power dissipation, good
active mode efficiency, and a variety of protection features.
The Need for PFC
Most electronic ballasts and switching power supplies use
a diode bridge rectifier and a bulk storage capacitor to
produce a dc voltage from the utility ac line. This produces
a non−sinusoidal current draw and places a significant
demand on the power delivery infrastructure. Increasingly,
government regulations and utility requirements often
necessitate control over line current harmonic content.
Active PFC circuits have become the most popular way to
meet these harmonic content requirements. They consist of
inserting a PFC pre−regulator between the rectifier bridge
and the bulk capacitor (Figure 1). The boost (or step−up)
converter is the most popular topology for active power
factor correction. With the proper control, it can be made to
produce a constant output voltage while drawing a
sinusoidal current from the line.
Rectifiers
PFC Preconverter
Converter
AC Line
High
+ Frequency
Bypass
Capacitor
NCP1606
+ Bulk
Storage
Capacitor
Load
Figure 1. Active PFC Stage with the NCP1606
Basic Operation of a CRM Boost Converter
For medium power (<300 W) applications, critical
conduction mode (CRM) is the preferred control method.
Critical conduction mode occurs at the boundary between
discontinuous conduction mode (DCM) and continuous
conduction mode (CCM). In CRM, the next driver on time
is initiated when the boost inductor current reaches zero.
Hence, CRM combines the lower peak currents of CCM
operation with the zero current switching of DCM
operation. But this control method means that the frequency
inherently varies with the line input voltage and the output
load. The operation and waveforms in a PFC boost converter
are illustrated in Figure 2. For detailed information on the
operation of a CRM Boost Converter for PFC applications,
please refer to AND8123 at www.onsemi.com.
© Semiconductor Components Industries, LLC, 2009
May, 2009 − Rev. 3
1
Publication Order Number:
AND8282/D
1 page  
AND8282/D
or IOVP = 10 mA (for NCP1606B)
Therefore, to achieve the desired maximum output
voltage with the NCP1606B, ROUT1 is equal to:
ROUT1
+
VOUT(max) * VOUT(nom)
IOVP
(eq. 10)
This gives a value of 4.0 MW for the NCP1606B or
1.0 MW for the NCP1606A.
ROUT2 is then sized to maintain 2.5 V on the FB pin when
Vout is at its targeted level.
ROUT2
+
2.5 V @ ROUT1
VOUT(nom) * 2.5
V
(eq. 11)
This gives a value of 25.2 kW for the B version or 6.3 kW
for the A version.
When determining the maximum output voltage level,
care must be exercised so as not to interfere with the natural
line frequency ripple on the output capacitor. This ripple is
caused by the averaging effect of the PFC stage: the current
charging the bulk cap is sinusoidal and in phase with the
input line, but the load current is not. The resultant ripple
voltage can be calculated as:
Vripple(pk*pk)
+
Cbulk
@
2
@
POUT
p @ fLINE
@
VOUT
(eq. 12)
where fLINE = 47 Hz (worst case for ripple)
A bulk capacitor value of 68 mF gives a peak to peak ripple
of 12.5 V. This is well below the peak output overvoltage
level (40 V).
The NCP1606 also incorporates undervoltage protection
(UVP). Under normal conditions, the boost output capacitor
will charge to the peak of the ac line. But if it does not charge
to some minimum voltage, then the NCP1606 enters
undervoltage protection. The minimum output voltage that
must be sensed is given by:
VoutUVP
+
ROUT1 ) ROUT2
ROUT2
@
VUVP
+
48.0
V
(eq. 13)
where VUVP = 300 mV (typ)
Note that this feature also provides protection against
open loop conditions in the feedback path. Consider that if
ROUT1 was inadvertently open (perhaps due to a bad solder
joint), the boost application would normally see that the FB
pin is too low (0 V in this case) and respond by delivering
maximum power. This could raise the output voltage well
above its maximum, potentially causing catastrophic
results. However, the NCP1606 incorporates a novel feature
which waits 180 ms at startup prior to issuing the first drive
pulse. Since the built in error amplifier would normally pull
FB to 2.5 V, the NCP1606 leaves the error amplifier disabled
during this time. If the FB pin is less than the UVP level
(300 mV), it continues to disable both the driver output and
the error amplifier. Thus, an undervoltage or open loop
condition can be always be accurately detected at startup
(Figure 6).
VCC(on)
VCC(off)
VCC
VOUT
VOUT(nom)
2.5 V
VUVP
VEAH
VEAL
FB
Control
UVP
UVP Fault is “Removed”
UVP Wait
UVP Wait
Figure 6. Timing Diagram Showing UVP and
Recovery from UVP
If the open loop event occurs after startup, then the fault
may not be detected immediately. This is because the error
amplifiers regulates the control pin to achieve 2.5 V on the
FB pin. Therefore, the FB voltage can only drop once the
maximum control pin voltage is achieved. When the FB
voltage drops below the UVP threshold, then the
undervoltage fault will be entered. The situation is depicted
in Figure 7.
VCC
VOUT
VOUT(nom)
FB
2.5 V
VUVP
ContVroEAl H
VEAL
VCC(on)
VCC(off)
ROUT1 is Opened
UVP
Figure 7. UVP Operation if ROUT1 is Opened After
Startup
http://onsemi.com
5
5 Page 
AND8282/D
Therefore, the Ct capacitor can be increased in size so that
the on time is a little longer near the zero crossing
(Figure 21). This also reduces the frequency variation over
the ac line cycle. The disadvantage to this approach is the
increased no load power dissipation created by RCTUP. The
designer must balance the desired THD and PF performance
with the no load power dissipation requirements.
Vac(t)
TON
with RCTUP
no RCTUP
no RCTUP
fSW with RCTUP
time
Figure 21. On Time and Switching Frequency With and Without RCTUP
The effect of this resistor on THD and power factor is illustrated in Figure 22.
25
20
15
Rctup = open
10
Rctup = 1.5 MW
5
0
85 115 145 175 205 235 265
Vac (Vrms)
Figure 22. Effect of Rctup on Full Load
(100 W) THD
2. Improve the THD/PF at Light Load or High Line:
If the required on time at light load or high line is less than
the minimum on time, then the controller will deliver too
much power. Eventually, this will cause the control voltage
to fall to its lowest level (VEAL). The controller will then
disable the drive (static OVP) to prevent the output voltage
from rising too high. Once the output drops lower, the
control voltage will rise and the cycle will repeat. Obviously,
this will add to the distortion of the input current and output
voltage ripple. However, there are two simple solutions to
remedy the problem:
1. Properly size the Ct capacitor. As mentioned
above, the capacitor must be large enough to
deliver the required on time at full load and low
line. However, sizing it too large means that the
range of control levels at light power will be
reduced. And as the Ct capacitor becomes larger,
the minimum on time of the driver will also
increase.
2. Compensate for propagation delays. If optimizing
the Ct capacitor still does not achieve the desired
performance, then it may be necessary to
compensate for the propagation delay. When the
Ct voltage exceeds the VCONTROL setpoint, the
PWM comparator sends a signal to end the on time
of the driver (Figure 23).
http://onsemi.com
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet AND8282D.PDF ] | |
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